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Hi,

When there is a stall, the BTB in the IF stage receives the same inputs several times and it can affect its prediction later. Therefore, the BTB needs to take it into account when there is a stall.

Best regards,
Kamal

Hi,
(Out of curiosity) I just generated the Verilog from your code and noticed that some of the generated wires have enormous width, i.e., wire [524318:0].
I suppose it's from the way you pick the shamt in line 60. By doing so, you are, in theory, able to shift by 2^19 bits.
There is probably some way to restrict the destination width. If you have time, you can take a look.
Best regards,
Lucas