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cache-model

core-v-verif

Fork of CORE-V verification environment to be used with a RISC-V vector processor based on CVE2 (CORE-V) and Spatz (PULP)

cv32e20v

Repository for adding RISC-V vector extension (Zve32x) support to the CVE2 RISC-V scalar core from the OpenHW group. The vector unit called Spatz is used from the PULP platform.

cve2x

A fork to implement the X accelerator interface for CVE2

ddr5_phy

Verification of digital data path of DDR5 PHY -- Graduation project under supervision of Si-Vision

hammer_vector

Using Hammer (interface to the Spike ISA simulator) for simulation of RISCV Vector code (Zve)

min-cut-floorplan-algorithm

payment-application-simulation-of-system-

risc-v-m-extension-coprocessor-for-picorv32-core

RISC-V M-Extension Coprocessor for PicoRV32 Core

riscv-core

Adding Branch Prediction to RISCV-Core

riscv_vector_zve_ppa

PPA Estimation/Optimization of RISCV Zve Vector Extension

rsa-accel

RSA accelerator based on Montgomery's algorithm

spatz

A fork to complete the missing instructions from the RISC-V Zve32X vector extension

traffic-light-control-application

Application to control a traffic lights system with an on-demand crosswalk button.

vicuna

RISC-V Zve32x Vector Coprocessor