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License: MIT License
Description of Chinese SM3 Hash algorithm with Verilog HDL
License: MIT License
Hello, I would like to use this SM3 module as an IP to integrate into my SOC. Data needs to be transmitted to this module through the bus. In the testbench you provided, add msg_ Valid_ After the in is raised, each rising edge SM3 of the clock will read the message and expand it. But the transmission speed of my bus is not enough to update data at each clock. How does this need to be resolved?
Too much data can not be used, will lose input data
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