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parametrizable-floating-point-verilog

Verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent

pastilda

open-source password manager

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

protothreads-cpp

Protothread.h, a C++ port of Adam Dunkels' protothreads library

python-telegram-bot

We have made you a wrapper you can't refuse

quickpid

A fast PID controller with multiple options. Various Integral anti-windup, Proportional, Derivative and timer control modes.

red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

static_vector

C++ static vector class template. Also might be known as fixed vector or on-stack vector.

surf

A huge VHDL library for FPGA development

tcl_for_fpga

TCL scripts for FPGA (Xilinx)

utils

Utilities for C++ for Embedded

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

verilog-axi

Verilog AXI components for FPGA implementation

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-dsp

Verilog digital signal processing components

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-flowgen

Ethernet flow generator framework

verilog-lfsr

Fully parametrizable combinatorial parallel LFSR/CRC module

verilog-pcie

Verilog PCI express components

vextproj

VEXTPROJ - the version control friendly system for creation of Vivado projects

vitis-hls-introductory-examples

vitis-tutorials

Vitis In-Depth Tutorials

vitis_accel_examples

Vitis_Accel_Examples

vitis_with_100gbps_tcp-ip

100 Gbps TCP/IP stack for Vitis shells

vivado-git

A git-friendly Vivado wrapper

vivadoscripting

Python Utilities to use Xilinx Vivado Tools from Python Scripts

wb2axip

Bus bridges and other odds and ends

wpseyes

Tool for bruteforce Wi-Fi WPS