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mfkiwl potatoe88888 jiijkkk tang-haojin zj2089 zeal4u good-circle rvcore 00light00 huanglingfeng gravelcai jian-fang cyril0124 siudya maxpicca-li love-tolstoy fuwenyi ruiszhang huangliwood bnweee himalsubedi787 yu-yake2002 sumailyyc euphgh spinech0 r-eajks cyyselfhuancun's Issues
请教一下关于接入Non-inclusive HuanCun作为L2 Cache Probe的问题
您好，想请教以下两个问题：
1.L2 HuanCun在什么情况下会向L1发送Probe请求？我目前只了解到，当一个L1 Cache的最新副本存在另一个L1 Cache时，L2 Cache会向另一个L1 Cache发出Probe请求。想问一下还有哪些情况会让HuanCun向Client Cache 发出Probe?
2.当进行Probe事务时，HuanCun 用什么方式告诉L1 Cache 需要ProbeAckData? (即L1 Cache ProbeAck的时候是否需要返回Data)。我正在尝试自己实现一个L1 Cache与Huancun连接，对于Probe请求，我目前使用的方式是在L1中通过onProbe函数判断是否有脏数据，若有则向Huancun返回Data，不过这个方式好像并不适配。
非常感谢~
关于TL--CHI协议
你好，想问一下，咱们目前昆明湖的设计中，总线协议是片内采用TileLink，片外采用CHI协议吗，之前说昆明湖准备替换TileLink为CHI，目前看到TL转CHI的bridge开发，这样的话，核间核内是保留了Tilelink协议然后通过Bridge，外设总线采用CHI的方案吗？
rocket-chip submodule使用https进行clone
Hi,
提个小建议，可否将.gitmodules中的rocket-chip改为https协议？以便支持匿名clone。
Thanks~
请教关于skipProbeN
MetaData中的skipProbeN有些不明白，请教一下
def skipProbeN(opcode: UInt): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed
// Put => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get
}
这个方法似乎是判断对于某个client的请求，是否需要probe它自己，既然它自己发出了Put请求为什么还需要probe它自己，即便是它可能拥有B权限的数据，也不应该需要再probe呀？另外hint为啥要还要probe也不太明白。
谢谢
请教关于core_reset的问题
在huancun/CtrlUnit.scala有一个改动是这样的
remove reset of all cores initially:
- val core_reset = RegInit(0.U(64.W)) +:Seq.fill(wrapper.num_cores-1){ RegInit(1.U(64.W)) }
- val core_reset = Seq.fill(wrapper.num_cores){ RegInit(0.U(64.W)) }
例如一个双核，如果都取消了复位，那一个程序会直接进入两个核同时执行，而不是像之前先进入主核执行，请问这是出于什么考虑呢？谢谢！
请教有关多核原子操作的问题
在双核中L3cache是共享的，原子指令在dcache中处理，以双核为例，当core0使用lr对某一地址进行标记后，若在sc指令之前，core1对同一地址进行store类操作，core0的sc应该失败，那在共享的L3cache中是怎么实现原子指令标志相关信息的共享的呢？谢谢！
make test error, tried with java 1.8.0_292 and java 11, ubuntu16.04
VirtualBox:~/cache_str/HuanCun$ make test
mill -i HuanCun.test.test
[164/164] HuanCun.test.test
====== Non-inclusive L2 (32.0KB * 1-bank) prefetch: true ======
bankBits: 0
sets:128 ways:4 blockBytes:64
[client] size:16.0KB
[client] sets:32 ways:8 blockBytes:64
usr/needHint: (1-bit)
usr/preferCache: (1-bit)
clientBits: 1
Data ECC bits:0
Tag ECC bits:0
Tag ECC bits:0
0 <= L1D-bank0
1 <= L1I-bank0
2 <= PTW-bank0
AllocatorTest:
L2
huancun.AllocatorTest *** ABORTED ***
java.lang.NoClassDefFoundError: chisel3/MultiIOModule
at chiseltest.internal.VerilatorBackendAnnotation$.(Testers2.scala:127)
at chiseltest.internal.VerilatorBackendAnnotation$.(Testers2.scala)
at chiseltest.experimental.ChiselTestCli.$init$(ChiselTestShell.scala:16)
at chiseltest.experimental.ChiselTestShell.(ChiselTestShell.scala:22)
at chiseltest.ChiselScalatestTester$TestBuilder.apply(ChiselScalatestTester.scala:26)
at huancun.AllocatorTest.$anonfun$new$2(AllocatorTest.scala:19)
at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23)
at org.scalatest.OutcomeOf.outcomeOf(OutcomeOf.scala:85)
at org.scalatest.OutcomeOf.outcomeOf$(OutcomeOf.scala:83)
at org.scalatest.OutcomeOf$.outcomeOf(OutcomeOf.scala:104)
...
Cause: java.lang.ClassNotFoundException: chisel3.MultiIOModule
at java.net.URLClassLoader.findClass(URLClassLoader.java:382)
at mill.api.ClassLoader$$anon$1.findClass(ClassLoader.scala:43)
at java.lang.ClassLoader.loadClass(ClassLoader.java:418)
at java.lang.ClassLoader.loadClass(ClassLoader.java:351)
at chiseltest.internal.VerilatorBackendAnnotation$.(Testers2.scala:127)
at chiseltest.internal.VerilatorBackendAnnotation$.(Testers2.scala)
at chiseltest.experimental.ChiselTestCli.$init$(ChiselTestShell.scala:16)
at chiseltest.experimental.ChiselTestShell.(ChiselTestShell.scala:22)
at chiseltest.ChiselScalatestTester$TestBuilder.apply(ChiselScalatestTester.scala:26)
at huancun.AllocatorTest.$anonfun$new$2(AllocatorTest.scala:19)
...
java.lang.NoClassDefFoundError: chisel3/MultiIOModule
java.lang.NoClassDefFoundError: chisel3/MultiIOModule
at chiseltest.internal.VerilatorBackendAnnotation$.(Testers2.scala:127)
at chiseltest.internal.VerilatorBackendAnnotation$.(Testers2.scala)
at chiseltest.experimental.ChiselTestCli.$init$(ChiselTestShell.scala:16)
at chiseltest.experimental.ChiselTestShell.(ChiselTestShell.scala:22)
at chiseltest.ChiselScalatestTester$TestBuilder.apply(ChiselScalatestTester.scala:26)
at huancun.AllocatorTest.$anonfun$new$2(AllocatorTest.scala:19)
at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23)
at org.scalatest.OutcomeOf.outcomeOf(OutcomeOf.scala:85)
at org.scalatest.OutcomeOf.outcomeOf$(OutcomeOf.scala:83)
at org.scalatest.OutcomeOf$.outcomeOf(OutcomeOf.scala:104)
at org.scalatest.Transformer.apply(Transformer.scala:22)
at org.scalatest.Transformer.apply(Transformer.scala:20)
at org.scalatest.flatspec.AnyFlatSpecLike$$anon$5.apply(AnyFlatSpecLike.scala:1684)
at org.scalatest.TestSuite.withFixture(TestSuite.scala:196)
at org.scalatest.TestSuite.withFixture$(TestSuite.scala:195)
at huancun.L2Tester.chiseltest$ChiselScalatestTester$$super$withFixture(L2Tester.scala:13)
at chiseltest.ChiselScalatestTester.$anonfun$withFixture$1(ChiselScalatestTester.scala:50)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
at chiseltest.ChiselScalatestTester.withFixture(ChiselScalatestTester.scala:50)
at chiseltest.ChiselScalatestTester.withFixture$(ChiselScalatestTester.scala:47)
at huancun.L2Tester.withFixture(L2Tester.scala:13)
at org.scalatest.flatspec.AnyFlatSpecLike.invokeWithFixture$1(AnyFlatSpecLike.scala:1682)
at org.scalatest.flatspec.AnyFlatSpecLike.$anonfun$runTest$1(AnyFlatSpecLike.scala:1694)
at org.scalatest.SuperEngine.runTestImpl(Engine.scala:306)
at org.scalatest.flatspec.AnyFlatSpecLike.runTest(AnyFlatSpecLike.scala:1694)
at org.scalatest.flatspec.AnyFlatSpecLike.runTest$(AnyFlatSpecLike.scala:1676)
at org.scalatest.flatspec.AnyFlatSpec.runTest(AnyFlatSpec.scala:1685)
at org.scalatest.flatspec.AnyFlatSpecLike.$anonfun$runTests$1(AnyFlatSpecLike.scala:1752)
at org.scalatest.SuperEngine.$anonfun$runTestsInBranch$1(Engine.scala:413)
at scala.collection.immutable.List.foreach(List.scala:431)
at org.scalatest.SuperEngine.traverseSubNodes$1(Engine.scala:401)
at org.scalatest.SuperEngine.runTestsInBranch(Engine.scala:390)
at org.scalatest.SuperEngine.$anonfun$runTestsInBranch$1(Engine.scala:427)
at scala.collection.immutable.List.foreach(List.scala:431)
at org.scalatest.SuperEngine.traverseSubNodes$1(Engine.scala:401)
at org.scalatest.SuperEngine.runTestsInBranch(Engine.scala:396)
at org.scalatest.SuperEngine.runTestsImpl(Engine.scala:475)
at org.scalatest.flatspec.AnyFlatSpecLike.runTests(AnyFlatSpecLike.scala:1752)
at org.scalatest.flatspec.AnyFlatSpecLike.runTests$(AnyFlatSpecLike.scala:1751)
at org.scalatest.flatspec.AnyFlatSpec.runTests(AnyFlatSpec.scala:1685)
at org.scalatest.Suite.run(Suite.scala:1112)
at org.scalatest.Suite.run$(Suite.scala:1094)
at org.scalatest.flatspec.AnyFlatSpec.org$scalatest$flatspec$AnyFlatSpecLike$$super$run(AnyFlatSpec.scala:1685)
at org.scalatest.flatspec.AnyFlatSpecLike.$anonfun$run$1(AnyFlatSpecLike.scala:1797)
at org.scalatest.SuperEngine.runImpl(Engine.scala:535)
at org.scalatest.flatspec.AnyFlatSpecLike.run(AnyFlatSpecLike.scala:1797)
at org.scalatest.flatspec.AnyFlatSpecLike.run$(AnyFlatSpecLike.scala:1795)
at org.scalatest.flatspec.AnyFlatSpec.run(AnyFlatSpec.scala:1685)
at org.scalatest.tools.Framework.org$scalatest$tools$Framework$$runSuite(Framework.scala:318)
at org.scalatest.tools.Framework$ScalaTestTask.execute(Framework.scala:513)
at mill.scalalib.TestRunner$.$anonfun$runTestFramework$2(TestRunner.scala:251)
at mill.modules.Jvm$.inprocess(Jvm.scala:254)
at mill.scalalib.TestRunner$.runTestFramework(TestRunner.scala:214)
at mill.scalalib.TestRunner$.main(TestRunner.scala:162)
at mill.scalalib.TestRunner.main(TestRunner.scala)
Caused by: java.lang.ClassNotFoundException: chisel3.MultiIOModule
at java.net.URLClassLoader.findClass(URLClassLoader.java:382)
at mill.api.ClassLoader$$anon$1.findClass(ClassLoader.scala:43)
at java.lang.ClassLoader.loadClass(ClassLoader.java:418)
at java.lang.ClassLoader.loadClass(ClassLoader.java:351)
... 55 more
1 targets failed
HuanCun.test.test Test execution failed.
Makefile:9: recipe for target 'test' failed
make: *** [test] Error 1
请教关于缓存中T权限的设计
您好，我发现在L1Cache中请求NtoB,很多情况下L2cache的D通道会自动升权到toT响应，在Dcache中应该是没问题的，但是在多核ICache情况在，ICache正常情况下应该只读，但是T权限是可读可写，那按我的理解多核情况下icache频繁的probe toB,那这样性能上是不是会有问题呢？请问当时设计的promoteT是基于哪些方面的考虑呢？谢谢！
关于TileLink协议
请教一下，咱们目前核内和缓存按照TileLink协议，这个协议对于后续更多核的设计和高性能设计有局限性吗？ 后续是否考虑一直延续使用这个协议？
请教一下为什么总线协议从Tilelink转向了CHI？
最近看香山双周报，总线协议都在推进CHI协议，想问下，为什么要转吗？
请教一下有关noninclusive 和inclusive的问题
您好，我从更新的缓存代码里发现你们主要更新的是noninclusive策略的代码，并未过多关注和修改inclusive部分，这是出于什么考虑呢？noninclusive相比而言有什么具体优劣呢？谢谢
can i create slavenodes to replace the ram.nodes in the testtop?
Here is my code:
.......
def createManagerNode = {
val slaveNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = Seq(AddressSet(0xL, 0xffffL)),
regionType = RegionType.UNCACHED,
resources = new SimpleDevice("l2", Seq("sifive,maskl2")).reg("mem"),
executable = true,
supportsGet = TransferSizes(1, cacheParams.blockBytes),
supportsPutPartial = TransferSizes(1, cacheParams.blockBytes),
supportsPutFull = TransferSizes(1, cacheParams.blockBytes),
fifoId = Some(0)
)),
beatBytes = cacheParams.blockBytes
)
))
slaveNode
}
....
val slave_nodes = createManagerNode
...
for(l1d <- l1d_nodes){
xbar := TLBuffer() := l1d
}
slave_nodes :=
TLXbar() :=*
TLFragmenter(32, 64) :=*
TLCacheCork() :=*
TLDelayer(delayFactor) :=*
l2.node :=* xbar
lazy val module = new LazyModuleImp(this){
master_nodes.zipWithIndex.foreach{
case (node, i) =>
node.makeIOs()(ValName(s"master_port_$i"))
}
slave_nodes.makeIOs()(ValName(s"s_port"))
}
}
====================
the problems are as follows:
====== Non-inclusive L2 (32.0KB * 1-bank) prefetch: None ======
bankBits: 0
sets:128 ways:4 blockBytes:64
[client] size:16.0KB
[client] sets:32 ways:8 blockBytes:64
blockGranularityBits: 5
usr/needHint: (1-bit)
usr/preferCache: (1-bit)
usr/alias: (2-bit)
echo/blockisdirty: (1-bit)
Exception in thread "main" java.lang.IllegalArgumentException: requirement failed
at ... ()
at huancun.HuanCun$$anon$1.$anonfun$slices$2(HuanCun.scala:321)
at scala.collection.immutable.List.map(List.scala:293)
at huancun.HuanCun$$anon$1.$anonfun$slices$1(HuanCun.scala:319)
at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
at huancun.HuanCun$$anon$1.(HuanCun.scala:319)
at huancun.HuanCun.$anonfun$module$1(HuanCun.scala:233)
at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
at huancun.HuanCun.module$lzycompute(HuanCun.scala:233)
at huancun.HuanCun.module(HuanCun.scala:233)
at huancun.HuanCun.module(HuanCun.scala:170)
at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$3(LazyModule.scala:278)
at chisel3.Module$.do_apply(Module.scala:53)
at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$2(LazyModule.scala:278)
at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:278)
at scala.collection.immutable.List.flatMap(List.scala:366)
at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:276)
at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:273)
at freechips.rocketchip.diplomacy.LazyModuleImp.instantiate(LazyModule.scala:335)
....
请教Huancun模块如何与DRAMsim集成并仿真测试
香山团队的老师同学你们好，我看到像RandomTest等仿真类使用TLRAM作为内存，但是并不能反映出像DDR控制器中的行为，所以想请教一下如何将Huancun模块（单独的Huancun模块，不包括处理器核心，否则整个过程有点繁杂了）与DRAMsim联合仿真？
有关TL-test用于TileLink香山核内核间一致性验证问题
您好，想问一下，看目前的香山项目，都是使用TL-test来验证TileLink在处理核内核间数据一致性功能是否有bug，看以前的报告中提到，TL-test不仅仅能用于系统级（针对L2的验证）、模块级（针对L2-L3的验证），还能用于SoC级别的验证，看目前南湖代码，好像是只有模块级和系统级的TL-test验证引用，请问在那里能看到针对SoC级别上TL-test对TileLink的验证应用？
此外，我还有一个问题，看代码，目前咱们的南湖架构，在核内使用TileLink协议，那么在与核外的peripheral连接时，是使用TileLink Bridge AXI/AHB等与商用ARM高速总线互连后在和peripheral交互么？
感谢解答！
make verilog with huancun.compile Compilation failed
make verilog
mkdir -p build
mill -i XiangShan.runMain top.TopMain -td build \
--config DefaultConfig --full-stacktrace --output-file XSTop.v \
--disable-all --remove-assert --infer-rw \
--repl-seq-mem -c:top.TopMain:-o:build/XSTop.v.conf \
--gen-mem-verilog full \
--num-cores 1
[180/243] huancun.compile
[info] compiling 45 Scala sources to /home/pi/XiangShan/out/huancun/compile/dest/classes ...
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:6:8: not found: object freechips
[error] import freechips.rocketchip.diplomacy._
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:7:8: not found: object freechips
[error] import freechips.rocketchip.tilelink._
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:8:8: not found: object freechips
[error] import freechips.rocketchip.util.BundleField
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:15:38: not found: type TLCustomNode
[error] )(implicit valName: ValName) extends TLCustomNode {
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:13:17: not found: type TLMasterPortParameters
[error] clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:13:44: not found: type TLMasterPortParameters
[error] clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:14:18: not found: type TLSlavePortParameters
[error] managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:14:44: not found: type TLSlavePortParameters
[error] managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:15:21: not found: type ValName
[error] )(implicit valName: ValName) extends TLCustomNode {
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:22:72: not found: type TLClientPortParameters
[error] override def mapParamsD(n: Int, p: Seq[TLClientPortParameters]): Seq[TLClientPortParameters] = {
[error] ^
[warn] /home/pi/XiangShan/huancun/src/main/scala/huancun/Slice.scala:412:44: non-variable type argument huancun.noninclusive.MSHR in type pattern Seq[huancun.noninclusive.MSHR] (the underlying of Seq[huancun.noninclusive.MSHR]) is unchecked since it is eliminated by erasure
[warn] case (dir: noninclusive.Directory, ms: Seq[noninclusive.MSHR]) =>
[warn] ^
[warn] /home/pi/XiangShan/huancun/src/main/scala/huancun/Slice.scala:427:38: non-variable type argument huancun.inclusive.MSHR in type pattern Seq[huancun.inclusive.MSHR] (the underlying of Seq[huancun.inclusive.MSHR]) is unchecked since it is eliminated by erasure
[warn] case (_: inclusive.Directory, _: Seq[inclusive.MSHR]) =>
[warn] ^
[warn] two warnings found
[error] 460 errors found
1 targets failed
huancun.compile Compilation failed
make: *** [Makefile:48：build/XSTop.v] 错误 1
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