nobodywasishere / vhdlproc Goto Github PK

The VHDL standard (IEEE Std. 1076-20**) has tool directives in clause 24. You could use the '`' character instead of '#' and be compliant with the VHDL standard. Moreover, in IEEE Std 1076-2019, a new feature called conditional analysis was added. See Clause 24.2 for more details.

This is the an EBNF based summary:

More details can be found here: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/LCS2016_061

In your documentation, please be sure to note what is a VHDL-2019 directive vs. what are your extensions.

In particular, please be sure to note that `define and `include are your extensions.

If you think your extensions should be part of the standard, then participate.
We also use git for our issues. See:
https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues

Furthermore, if you are capable of writing a tool like this and you use git,
you would be a valuable asset to the team - yes we recruit people from
the open source community :)

Currently, to use VHDLproc, you have to either process each file to another file (and then run ghdl, etc on those files), or do everything in python, passing around the code as text instead of files.
It would be better if it operated like this:

vhdlproc *.vhd
ghdl -a *.vhd # same files
# next run a testbench, synthesize using yosys, etc.

But of course, this modifies the source files meaning the preprocess is only run once.

Potential solutions/ideas:

• Have vhdlproc read/process directives in comments as well, allowing for reevaluation (violates vhdl-2019, may be confusing to use)
• Process, save to a temp directory, and return a list of the files that can be then passed to another command, ghdl -a $(vhdlproc --tmp -f *.vhd)
• Integrate directly into the ghdl analysis/elaborate process, but this may be complicated and wouldn't help those tools who can't be modified

Unsure which option to implement, feedback welcome.