Incorrect byte order for multibyte DIN packets about linuxcnc-rio HOT 9 CLOSED

I think the bracket issue is not in the dout part because there are no '-not' pin name's

i'm in the office now, i will check the digital io's later at home

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Just checked you are correct about the dout.

Just cleaned up my local and pushed to my repo.

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ok, i see the problem, grrrrr, brainf*** :p

assign tx_data = {
    header_tx[7:0], header_tx[15:8], header_tx[23:16], header_tx[31:24],
    jointFeedback0[7:0], jointFeedback0[15:8], jointFeedback0[23:16], jointFeedback0[31:24],
    jointFeedback1[7:0], jointFeedback1[15:8], jointFeedback1[23:16], jointFeedback1[31:24],
    jointFeedback2[7:0], jointFeedback2[15:8], jointFeedback2[23:16], jointFeedback2[31:24],
    jointFeedback3[7:0], jointFeedback3[15:8], jointFeedback3[23:16], jointFeedback3[31:24],
    jointFeedback4[7:0], jointFeedback4[15:8], jointFeedback4[23:16], jointFeedback4[31:24],
    processVariable0[7:0], processVariable0[15:8], processVariable0[23:16], processVariable0[31:24],
    DIN15, DIN14, DIN13, DIN12, DIN11, DIN10, DIN9, DIN8, DIN7, DIN6, DIN5, DIN4, DIN3, DIN2, DIN1, DIN0
};

first i have to reorder the DIN's in verilog

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ok, hope i have fix it now , please can you test it ?

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Fantastic, works like a charm. Tested with 17 inputs, ie: 3 packets.

Python is a bit exotic to me. Tho I should learn.
Just got my Olimex ICE40HK8X-EVB, as I want to keep the Lattice board for future experiments, so that will be the weekends' project.
Still waiting on the Eth to Spi board.

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Not related to this topic but, I was wondering if LiteEth can be used instead of an an Eth to Spi board.

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Doesn't LiteEth require a soft core ?

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I am too new to FPGA's and the litex tools. I looked at the liteeth repository but could not determine, whether Its uses a soft core.
Hey Rob I am also in the Sydney area!

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my verilog knowledge is rather limited,
so I wanted to keep this part as simple as possible.

lite eth probably uses a softcore for the ethernet.

but i think it's ok to use a MCU in this place and the spi interface keeps the delay quite low.

if someone can do the ethernet without softcore i would be happy about pullrequests :)

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