Comments (3)
Scrubbing stale issues. @eunchan what's the current status? Thanks.
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d_user
is still not a struct yet. Other items were completed.
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The last item (d_user_t
) was added by Tim in February with d12569f.
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Related Issues (20)
- [usbdev] OUT side STALL response can leave device unable to capture next SETUP/OUT packet HOT 5
- [dvsim] Question about running gate-level simulation on VCS HOT 1
- [test-triage] HMAC rand seq with test vector tests
- [test-triage] i2c_target_tx_stretch_ctrl failure after b2f07af
- [test-triage] i2c_csr_bit_bash assertion failure `TxWriteStableBeforeHandshake_A` HOT 1
- [dvsim] Issue with Gate Level Simulation using SDF File
- [csrng/dv] Verify RESEED_COUNTER_X and INT_STATE_VAL CSRs HOT 2
- [csrng/dv] Verify INT_STATE_READ_ENABLE CSR HOT 1
- [entropy_src] change of HEALTH_TEST_WINDOWS.FIPS_WINDOW and watermarks HOT 1
- [RFC] Release, Branching and ECO Process HOT 1
- [usbdev] prim_cdc_rand_delay induces sampling errors with usb_fs_rx HOT 2
- [hmac,dv] Reduce reseeding of long HMAC SHA-2/HMAC test vectors tests HOT 1
- [rom] Audit accesses to CSRs with CDCs HOT 3
- [csrng] Return error status response for GEN commands with glen = 0
- [rom,e2e] enforce banner check in FPGA test
- [dvsim] Question: Where to find a handbook including all the keywords available in hjson and core file
- [test-triage] Flaky i2c_tl_intg_err
- [rom_ext] BootLog incorrect for currently executing ROM_EXT slot
- [rom_ext] Try to boot other slot if primary is un-bootable HOT 1
- [hmac,dv] FIFO status to be cycle accurate
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