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mastering_digital_design's Introduction

Mastering Digital Design

This is the webpage for the MSc ADIC lab on "Mastering Digital Design".

Please send feedback on any of this material (e.g. errors, typos, or other suggestions for improvement) to Dr Wickerson. You can either do this by raising an issue or by emailing him.

Aims

  1. To ensure all students on the MSc course reach a common competence level in RTL design using FPGAs in a hardware description language; and
  2. To act as revision exercise for those who are already competent in Verilog and FPGA.

You will conduct this experiment in the first half of the Autumn Term. You can find a copy of the Experiment Specification Document here.

Learning Outcomes

This Lab Experiment has FOUR distinct parts, each with specific learning outcomes.

Part 1: Basic competence in using Intel/Altera’s Quartus design systems for Cyclone-V FPGA; appreciate the superiority of hardware description language over schematic capture for digital design; use of case statement to specify combinatorial circuit; use higher level constructs in Verilog to specify complex combinatorial circuits; develop competence in taking a design from description to hardware.

Part 2: Use Verilog to specify sequential circuits; design of basic building blocks including: counters, linear-feedback shift-registers to generate pseudo-random numbers, basic state machines; using enable signals to implement globally synchronisation.

Part 3: Understand how digital components communicate through synchronous serial interface; interfacing digital circuits to analogue components such as ADC and DAC; use of block memory in FPGAs; number system and arithmetic operations such as adders and multipliers; digital signal generation.

Part 4: Understand how to implement a FIFO using counters as pointer registers and Block RAM as storage; implement a relatively complex digital circuit using different building blocks including: counters, finite state machines, registers, encoder/decoder, address computation unit, memory blocks, digital delay elements, synchronisers etc.; learn how to debug moderately complex digital circuits.

Assessment

There will be an oral interview at the end of the experiment. The marks for this experiment will count towards the Coursework component of the MSc course.

Experiment

The experiment handbook can be found here. Below are some useful resources for each part of the experiment.

Part 1: Schematic vs. Verilog

Part 2: Counters and FSMs

Part 3: DAC and Tone Generator

Part 4: ADC/DAC and Echo Synthesiser

Lectures

Other reference material

DE1-SoC Reference Manuals

Cyclone V Device Handbooks

Quartus Related Links

Verilog Resources

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mastering_digital_design's Issues

Procuring cables for the course.

Last session I provided the present students with male-male 3.5mm jacks for the experiment taken from 905 labs own supply. In future, I think this should be made a requirement for EEE stores to provide this and 3.5mm headphones because these are necessary to complete the course but are somewhat obsolete and unlikely for students to have with them.

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