This is the webpage for the MSc ADIC lab on "Mastering Digital Design".

• Lab leader: Dr John Wickerson.
• Course originally developed by: Prof Peter Cheung.
• Teaching assistants 2022: Mr Jianyi Cheng and Mr Benjamin Biggs.

Please send feedback on any of this material (e.g. errors, typos, or other suggestions for improvement) to Dr Wickerson. You can either do this by raising an issue or by emailing him.

1. To ensure all students on the MSc course reach a common competence level in RTL design using FPGAs in a hardware description language; and
2. To act as revision exercise for those who are already competent in Verilog and FPGA.

You will conduct this experiment in the first half of the Autumn Term. You can find a copy of the Experiment Specification Document here.

This Lab Experiment has FOUR distinct parts, each with specific learning outcomes.

Part 1: Basic competence in using Intel/Altera’s Quartus design systems for Cyclone-V FPGA; appreciate the superiority of hardware description language over schematic capture for digital design; use of case statement to specify combinatorial circuit; use higher level constructs in Verilog to specify complex combinatorial circuits; develop competence in taking a design from description to hardware.

Part 2: Use Verilog to specify sequential circuits; design of basic building blocks including: counters, linear-feedback shift-registers to generate pseudo-random numbers, basic state machines; using enable signals to implement globally synchronisation.

Part 3: Understand how digital components communicate through synchronous serial interface; interfacing digital circuits to analogue components such as ADC and DAC; use of block memory in FPGAs; number system and arithmetic operations such as adders and multipliers; digital signal generation.

Part 4: Understand how to implement a FIFO using counters as pointer registers and Block RAM as storage; implement a relatively complex digital circuit using different building blocks including: counters, finite state machines, registers, encoder/decoder, address computation unit, memory blocks, digital delay elements, synchronisers etc.; learn how to debug moderately complex digital circuits.

There will be an oral interview at the end of the experiment. The marks for this experiment will count towards the Coursework component of the MSc course.

The experiment handbook can be found here. Below are some useful resources for each part of the experiment.

• Ex1 solution
• Incomplete version of 7-segment decoder
• Pin assignment
• Verilog code for bin2bcd modules
• Ex4 solution

• Instructions for setting up ModelSim
• Ex8 solution
• Verilog code for bin2bcd modules
• Code for pwm

• spi2dac and spi2adc
• Explanation for spi2dac and spi3adc
• Test bench for spi2dac.v
• Analogue I/O Card schematic diagram
• DAC datasheet
• ADC datasheet
• Opamp datasheet
• Sinewave generation (python, matlab)
• ROM initialisation file
• Ex11 solution
• Ex14 solution
• Ex15 solution

• Ex16_proto
• Audio files (clapping.mp3, hello.mp3, hg2g_short.mp3, hg2g_full.mp3)
• Ex19 solution
• Ex20 solution

• Lecture 1 (Introduction)
• Lecture 2 (Clock circuits)
• Lecture 3 (PWM, FSM, and SPI)

• DE1-SoC Board from Terasic
• DE1-SoC Learning Roadmap
• DE1-SoC Getting Started Guide
• DE1-SoC My First FPGA
• DE1-SoC User's Manual
• DE1-SoC Schematic Diagram

• Cyclone V Device Overview
• Cyclone V Device Handbook Vol 1: Device Interfaces and Integration
• Cyclone V Device Handbook Vol 2: Transceivers
• Cyclone V Device Handbook Vol 3: Hard Processor System Technical Reference Manual

• Quartus Prime Lite Web Edition
• Quartus Tutorial Page

• Verilog tutorial by ASIC World