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CHIPYARD

Chipyard Framework CircleCI

Using Chipyard

To get started using Chipyard, see the documentation on the Chipyard documentation site: https://chipyard.readthedocs.io/

What is Chipyard

Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other Berkeley projects to produce a RISC-V SoC with everything from MMIO-mapped peripherals to custom accelerators. Chipyard contains processor cores (Rocket, BOOM, CVA6 (Ariane)), accelerators (Hwacha, Gemmini, NVDLA), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation (FireSim), automated VLSI flows (Hammer), and software workload generation for bare-metal and Linux-based systems (FireMarshal). Chipyard is actively developed in the Berkeley Architecture Research Group in the Electrical Engineering and Computer Sciences Department at the University of California, Berkeley.

Resources

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Contributing

Attribution and Chipyard-related Publications

If used for research, please cite Chipyard by the following publication:

@article{chipyard,
  author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar,   Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje},
  journal={IEEE Micro},
  title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs},
  year={2020},
  volume={40},
  number={4},
  pages={10-21},
  doi={10.1109/MM.2020.2996616},
  ISSN={1937-4143},
}
  • Chipyard
    • A. Amid, et al. IEEE Micro'20 PDF.
    • A. Amid, et al. DAC'20 PDF.
    • A. Amid, et al. ISCAS'21 PDF.

These additional publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs.

  • Generators
    • Rocket Chip: K. Asanovic, et al., UCB EECS TR. PDF.
    • BOOM: C. Celio, et al., Hot Chips 30. PDF.
      • SonicBOOM (BOOMv3): J. Zhao, et al., CARRV'20. PDF.
      • COBRA (BOOM Branch Prediction): J. Zhao, et al., ISPASS'21. PDF.
    • Hwacha: Y. Lee, et al., ESSCIRC'14. PDF.
    • Gemmini: H. Genc, et al., arXiv. PDF.
  • Sims
    • FireSim: S. Karandikar, et al., ISCA'18. PDF.
      • FireSim Micro Top Picks: S. Karandikar, et al., IEEE Micro, Top Picks 2018. PDF.
      • FASED: D. Biancolin, et al., FPGA'19. PDF.
      • Golden Gate: A. Magyar, et al., ICCAD'19. PDF.
      • FirePerf: S. Karandikar, et al., ASPLOS'20. PDF.
  • Tools
    • Chisel: J. Bachrach, et al., DAC'12. PDF.
    • FIRRTL: A. Izraelevitz, et al., ICCAD'17. PDF.
    • Chisel DSP: A. Wang, et al., DAC'18. PDF.
    • FireMarshal: N. Pemberton, et al., ISPASS'21. PDF.
  • VLSI
    • Hammer: E. Wang, et al., ISQED'20. PDF.

Acknowledgements

This work is supported by the NSF CCRI ENS Chipyard Award #201662.

chipyard's Projects

aes icon aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

artix-dc-scm icon artix-dc-scm

Experimental Xilinx Artix-7 driven Data Center Security Communication Module

asadbg icon asadbg

asadbg is a framework of tools to aid in automating live debugging of Cisco ASA devices

awsteria_infra icon awsteria_infra

"Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)

bsc icon bsc

Bluespec Compiler (BSC)

chipyard icon chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

clang-xpack icon clang-xpack

A binary xPack with the LLVM clang compiler infrastructure

cpu-fpga-briey icon cpu-fpga-briey

A CPU with full SoC implementation on FPGA based on Briey, plus UART demo.

cruvi icon cruvi

CRUVI Standard Specifications

daft icon daft

Automated Flasher Tester

darkriscv icon darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

de0_nano icon de0_nano

OpenRISC SOC for the De0 Nano FPGA dev board

deca-mandelbrot icon deca-mandelbrot

The Terasic DECA board as a mandelbrot accelerator via high speed USB

deca_board icon deca_board

Documentation and tools related to DECA FPGA board

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