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The ESP website contains the complete information on the ESP project. The documentation page contains detailed guides and video tutorials that will be released periodically to help users get the most out of ESP.

ESP is an open-source platform for heterogeneous SoC design and prototype on FPGA. It provides a flexible tile-based architecture built on a multi-plane network-on-chip.

In addition to the architecture, ESP provides users with templates and scripts to create new accelerators from SystemC, Chisel, and C. The ESP design methodology eases the integration process by offering platform services, such as DMA, distributed interrupt, and run-time coherence selection, that hide the complexity of hardware and software integration from the accelerator designer.

Currently, ESP supports multi-core Leon3 processor from GRLIB, based on the SPARC V8 32-bits ISA, and single-core Ariane processor from Pulp Platform, based on the RISC-V 64-bits ISA.

In addition to processor cores, ESP embeds accelerator design examples created with Stratus HLS in SystemC, and Chisel.

Furthermore, ESP can serve as a platform to integrate third-party IP blocks. As an example, ESP integrates the nvidia Deep Learning Accelerator NVDLA, which can be placed on any ESP accelerator tile.

• Multi-core Ariane RISC-V
• Automatic integration of accelerators generated with hls4ml from Keras/Tensorflow and Pytorch
• Support for Digilent Genesys2 FPGA board