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ahb-lite

AHB-Lite adapters, initiators and targets.

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

bdw

BSC Development Workstation (BDW)

bsc

Bluespec Compiler (BSC)

bsc-contrib

A place to share libraries and utilities that don't belong in the core bsc repo

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-template

A template project for beginning new Chisel work

documentation

Main page

ecc

Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrated Circuits.

esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

flute

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

hello-world

litedram

Small footprint and configurable DRAM core

liteeth

Small footprint and configurable Ethernet core

liteiclink

Small footprint and configurable Inter-Chip communication cores

litepcie

Small footprint and configurable PCIe core

litesata

Small footprint and configurable SATA core

litescope

Small footprint and configurable embedded FPGA logic analyzer

litesdcard

Small footprint and configurable SDCard core

litevideo

Small footprint and configurable video cores

litex

Build your hardware, easily!

litex-boards

LiteX boards files

origin

plsi

Palmer's VLSI scripts

riscv_debug_module

rocket-chip

Rocket Chip Generator

toooba

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT