intel / aib-phy-hardware Goto Github PK

Would it be possible to provide a reference GDS of the AIB bump locations and their corresponding text labels?

Hi,
I'd like to submit a mismatch issue from the AIB 1.2 spec, figure 42

vs the model code file rtl/aib_sm.v (line 510)

Would you please help to fix?

While compiling everything in multidie.f for Questa (Modelsim), I ran into several issues/errors.

1-The following files need to include the defines file c3dfx.vh by using `include "c3dfx.vh" at the top:
aib_lib/c3dfx/rtl/tcm/c3dfx_tcm_wrap.sv
aib_lib/c3aibadapt/rtl/c3aibadapt.v
aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1clk_ctl.v
aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm1.v
aib_lib/c3aibadapt/rtl/c3aibadapt_avmm/c3aibadapt_avmm.v
aib_lib/c3aibadapt/rtl/c3aibadapt_rxchnl/c3aibadapt_rxclk_ctl.v
aib_lib/c3dfx/rtl/tcb/c3dfx_aibadaptwrap_tcb.sv
aib_lib/c3aibadapt_wrap/rtl/c3aibadapt_wrap.v
ndsimslv/top.sv

2-In top.sv, dut.io must be replaced by top.io

3-In ndsimslv/nda_drv.sv, the following items must be commented out:

logic [2:0] csr_pipein;

reg pld_avmm1_clk_rowclk = 1'b0;
reg pld_avmm2_clk_rowclk = 1'b0;
reg pld_pma_coreclkin_rowclk = 1'b0;
reg pld_sclk1_rowclk = 1'b0;
reg pld_sclk2_rowclk = 1'b0;

logic [2:0] csr_config,
csr_in,
csr_pipe_in;
logic nfrzdrv_in;

4-In rtl/aib_ioring.v, the following wires need to be added:

wire [DATAWIDTH-1:0] nc_async_dat_poutp;
wire [DATAWIDTH-1:0] jtag_clkdr_outn_poutp;
wire [DATAWIDTH-1:0] nc_async_dat_pinp;
wire [DATAWIDTH-1:0] nc_odat_async_out0_pinp;
wire [DATAWIDTH-1:0] nc_oclk_out0_pinp;
wire [DATAWIDTH-1:0] nc_oclkb_out0_pinp;
wire [DATAWIDTH-1:0] nc_oclkn_out0_pinp;

ns_mac_rdy should go to AIB49 as an output from the S10 Chiplet. Please expose ns_mac_rdy as an input at each module port up through aib_top (where it will be ns_mac_rdy[23:0] to expose the signal from each channel).

Note that c3aibadapt sends aib_rx_pma_div66_clk into the aibcr3_top_wrap’s ihssi_pld_pma_clkdiv_rx_user input port. I think aibcr3_top_wrap’s ihssi_pld_pma_clkdiv_rx_user is the signal coming from AIB49 that should be brought out to aib_top and exposed as the input port ns_mac_rdy.

I don’t know what the aib_rx_pma_div66_clk wire does in c3aibadapt. But we have to break it in order to expose ihssi_pld_pma_clkdiv_rx_user up through aib_top. Would you also check that removing the aib_rx_pma_div66_clk does no harm?

Hi,
There is a warning of Select index out of bounds at line 2700 under rtl/aib_iorings.v
Seem that the idat0_poutp is not fully parameterized:

Could you please check again ?

2: should be tx_transfer_en
23: oad should be load
95: por should be power_on_reset

The bump spreadsheet
Stratix 10 Chiplet AIB Profile_v1_0_aib_bump_locations.xlsx
only contains master bump locations. Please add slave interface bump locations.

Hi,
Please help to check 4 connection issues below:

Tx and Rx both use the same port itxen to control in/out hence it made rxdat18 become X.

Wrong code is on 2133th line.
Right code should be on 2132th line.

: Wrong connection on iddren_in1 of rxfck/ rxfckb lead to wrong selection of iddren_out when running in repair mode.
Expectation: cell rxfck/ rxfckb keep iddren_out = 1 in repair mode.

Wrong code is on 1970th , 2554th line.
Right code should be on 1971th, 2555th line.

//aib_ioring

//aib_redundancy

//tb_top

similar issue with above issue with 2 more cells: rxclk/ rxclkb.
Fix: .iddren_in1(iddren), .ilaunch_clk_in0(vssl_aib).
Wrong code is on 1743th , 2325th line.
Right code should be on 1744th, 2326th line.

2 connection bugs on aib_ioring module of Intel model. (txdat8/ txdat9).

Fail reason:
As running SDR mode without repair function (mission mode), Intel will check condition iddren then if SDR mode => invert clk_in from m_ns_fwd_clk into ~m_ns_fwd_clk then assign it to txfcko (ns_fwd_clk).
// aib_ioring.v

But when running SDR mode with repair function, Intel forgot that condition (check iddren) and assign directly m_ns_fwd_clk to ns_fwd_clk.
-> It create a wrong latency (only 1.5clk not 2clks with SDR mode).
Wrong code is on 475th,476th / 1152th,1153th line.
Right code should be on 477th,478th / 1154th,1155th line.

Best regards,

Please help to fix the warning on the model:

Running on: how2use/sim_mod2mod
I modified below files:
tb_top.sv, line 18, DATAWIDTH =80;
tb_top.sv, line 356-357,
data[DATAWIDTH*2 -1:DATAWIDTH] = {$random,$random,$random};
data[DATAWIDTH -1:0] = {$random,$random,$random};

Then I got below warnings:

1- Warning-[PCWM-W] Port connection width mismatch
../../rtl/aib.v, 104
Warning-[PCWM-W] Port connection width mismatch
./tb_top.sv, 153
Warning-[PCWM-W] Port connection width mismatch
./tb_top.sv, 250

=> This is due to the fix 20-bit width of shift_en_tx/shift_en_rx” on redundancy_ctrl. The width of them should be defined based on DATAWIDTH parameter same as other signals.

2- Warning-[SIOB] Select index out of bounds
../../rtl/aib_ioring.v, 2700
=> boundary violation

3- Some concerns about port type declaration:
Lint-[PCTIO-L] Ports coerced to inout
../../rtl/aib_channel.v, 50
=> It should be declared as inout port?

Thanks

Hi,
As the AIB spec, sideband FSM should not be constrained by *adapter_rstn and *mac_rdy.
However, current model implementation having this constraint.
Would you please consider to fix this?

file: aib_channel.v

NOTE:

• ms_adapter_rstn is ns_adapter_rstn
• adapter_rsti is fs_adapter_rstn

Thanks

Calibration completion shall be indicated by the following signals:

• ms_tx_transfer_en
• ms_rx_transfer_en
• sl_tx_transfer_en
• sl_rx_transfer_en

Full completion shall be indicated when all four signals are asserted HI (Spec 3.2.3.3.5).
The simulation using the test bench shows that just the SL (sl_tx_transfer_en & sl_rx_transfer_en) signals are asserted HI and the test is passed. The MS (ms_tx_transfer_en & ms_rx_transfer_en) signals are initialized at LO and not asserted at HI. However, it does not change anything when I force the MS signals to HI.

"ms_tx_transfer_en & ms_rx_transfer_en (AIB Plus only) (Indicate that calibration on the master is complete for transmit and receive paths (Section 3.2.3.3))"

This is mean that one of the 2 calibration state machine is used specifically in this case the Slave to Master state machine (Spec Figure 41).

1. For all channels [23:0] expose the slave to master incoming shift register at aib_top, PHY-->MAC
2. For all channels [23:0] expose the master to slave bits corresponding to the outgoing shift register PHY-->MAC and MAC-->PHY
3. Identify the non-reserved bits in aib_top for my convenience :-), for example:
   wire sl_osc_transfer_en = sl_sideband[72];
   wire ms_tx_transfer_en = ms_sideband[78];

The aib_lib needs to identify in the code where hardened synchronizer flops should be used. For example in the file aibcr3_sync_3ff.v, the code should not be synthesized. Instead, this code should be contained within an
ifdef BEHAVIORAL and the else should contain a $display warning message -- this is where the technology dependent hardened flops should be entered.
RTL simulation then works with
+define+BEHAVIORAL
but synthesis will not produce a functional netlist until the `else section is filled in.

AIB open source uses two signals for resetting AIB adapter:
AIB61 u_adapter_tx_pld_rst_n
and
AIB65 u_adapter_rx_pld_rst_n

AIB spec says that a single reset
AIB65 fs_adapter_rstn
should cause the adapter to reset calibration.

Inside the open source the tx and rx adapter section are independently reset. This request is to perform both tx and rx functions based on AIB65. One possible means to do this is to edit c3aibadapt_wrap.v's c3aibadapt instantiation as follows:
As Is:
// Inputs
.i_aib_rx_adpt_rst_n (aib_rx_adpt_rst_n), // Templated
.i_aib_tx_adpt_rst_n (aib_tx_adpt_rst_n), // Templated
Edited
// Inputs
.i_aib_rx_adpt_rst_n (aib_rx_adpt_rst_n), // Templated
.i_aib_tx_adpt_rst_n (aib_rx_adpt_rst_n), // Templated

The desired result is that AIB61 is ignored, and AIB65 performs both a tx and rx adapter reset.

Hello Dave,

I am filling this out as a test case for you as requested in your email last week.

LMCO AIB PHY design used two files provided by Intel, 'dbg_test_defines.v' and 'dbg_test_jtagsm.v'. Neither of these files appear in your AIB repository.

Given that they are Intel based files, we need your approval to make them available publicly and to my knowledge, we cannot publicly release Intel based files through our GitHub.

I see two paths to getting this released in it's entirety, let me know if I am missing something here.

1. Intel reviews and posts the RTL as is to the Intel GitHub.
2. Intel reviews the items and approves us to remove any Intel markings and post to LMCO GitHub with no copyright markings.

I only propose #2 because the files originally did not have Intel markings on them when they were originally provided. Intrinsix added non-proprietary Intel headers in good faith to ensure they were not making a claim to your RTL.

Thank you,

• Isaac -

Intel Request.zip

Hi

I want to use this interface in my new project. Does this RTL code have been synthesis before. If it has been synthesis, can you tell me about your synthesis environment and how it is synthesis.

Thanks

The AIB specification RTL model is something that we would like to use within our emulation/FPGA environment. This is to support initial multi-die platform functional modeling, where, emulation/FPGA has the capacity to support larger models.

We are finding that the AIB fails on emulation compilation, one specific example is:
Error [RTLC-6775]: Fille: /nfs/site/disks/dcg_ifg/users/sncline/builds/sncline_t073_6aug2019/puma-rtl/HW/emu/../src/ebb/AIB/AIB_spec_IP/rtl/aib_ioring.v, Line 2598: Bit/Part/Concatenation select on nc_async_dat_poutp[i] is out of range. Continuing ...

We can help provide more specific/onion peeling confirmation of fixes needed since you might not have the lint checks/emulation checks needed to verify... Initial confirmation is to see if you are willing to work to make the AIB model emulation compliant.

User reported on 9/3/2019 that the MAC/PHY signal ns_mac_rdy is intercepted in the local adapter before it goes to the bump. The spec has this ns_mac_rdy description:
For resetting near-side data transfers and communicating MAC readiness for calibration to the far side

Please investigate how the ns_mac_rdy MAC/PHY signal is processed. If as the user says the signal is intercepted locally, we should not necessarily make any change as some designs expect the current behavior. This may be a "will not fix" issue.

Hi,
In the model, file aib_model/rtl/aib_aux_channel.v, there is 2 issue:

1. Device detect:
   it's refering directly to the iopad device_detect signal.
   We think it's better to have and port implemented to connect to the MAC.
   Suggestion to add line 20 and 39 in below picture:
   

2. POR signal
   In above picture, POR is create by and AND gate between the normal and redundancy signal.
   It's better to have OR gate implementation because we will want both POR stable 0 before claim
   the Power on reset is finished.
   Please help confirm if this understanding is correct.

Thank you and best regards,

The OR gate circuit with weak pull up cannot be driven into operational mode with por_ovrd. Document needs to be updated with AND gate.

The slave equivalent to
7.1.2 Alternate (Master) Channel Bump Map
is missing from the 1.2 spec.

At the aib_channel level we will need to have ms_data_fr_core and sl_data_fr_core be input of 81 bits and 73 bits as defined in the spec.
Otherwise the user field bits of the shift register can not be used form this model.

Please refer to 2.2.2 Sideband Control Signals section and table 11 in the spec 1.1

The AIB define that latency of DDR is 3UI (1.5 cycle) and SDR is 1UI (1 cycle)

But simulation on the open code showed that:

• DDR : TX have 3UI, but RX have 5UI
  
• SDR: 0.5UI

Please confirm.

The commented assigns below from from rtl/aib_channel.v don't seem to completely match Tables 50 and 51.

assign ms_data_fr_core[80:0] = {ms_osc_transfer_en,
1'b1,
ms_tx_transfer_en,
2'b11,
ms_rx_transfer_en,
ms_rx_dll_lock,
5'b11111,
ms_tx_dcc_cal_done,
1'b0,
1'b0, // Bit 66, AIB_Intel_Specification 1_2 Table 50 says '1'?
ms_external_cntl_65_8[57:0],
1'b1,
1'b0,
1'b0, // Bit 5, AIB_Intel_Specification 1_2 Table 50 says '1'?
ms_external_cntl_4_0[4:0]};

assign sl_data_fr_core[72:0] = {sl_osc_transfer_en,
1'b0,
sl_rx_transfer_en,
sl_rx_dcc_dll_lock_req,
sl_rx_dll_lock,
3'b0,
sl_tx_transfer_en,
sl_tx_dcc_dll_lock_req,
1'b0,
1'b0,
1'b0, // Bit 60, AIB_Intel_Specification 1_2 Table 51 says '1'?
1'b0,
1'b0, // Bit 58, AIB_Intel_Specification 1_2 Table 51 says '1'?
sl_external_cntl_57_32[25:0],
sl_tx_dcc_cal_done,
sl_external_cntl_30_28[2:0],
1'b0, sl_external_cntl_26_0[26:0]};

It seem that model (module aib_ioring.v) having a connection issue that leads to fail vector to run with DATAWIDTH = 80, SDR mode.

Version got issues: aib_20190826/
Running on: how2use/sim_mod2mod/
Modify: tb_top.sv, line 18, DATAWIDTH =80;
tb_top.sv, line 356-357,
data[DATAWIDTH*2 -1:DATAWIDTH] = {$random,$random,$random};
data[DATAWIDTH -1:0] = {$random,$random,$random};
tb_top.sv, line 214, .iddren(1'b0),
tb_top.sv, line 311, .iddren(1'b0),

iddren_in0/iddren_in1 are wrong connection as line 2760, 2761 and could be fix as line 2762, 2763

Before fix:

After fix:

Please help to check.
Thanks

Just confirming this works before we file a real ticket