Comments (2)
- Agree on the output. When in slave mode, device_detect should go from aib PHY to MAC. In the last few months we decided to call this PHY-->MAC signal "m_device_detect". As written this code cannot fully model the slave.
However, the code does not correctly model redundancy for device_detect. As slave, there is only 1 device_detect input buffer. No ANDing or ORing should be done. "For Slaves, the two device_detect bumps should be connected by Slave on-die wiring before the Slave input buffer." As master, there is only 1 device_detect output buffer. "For Masters, the two device_detect bumps should be connected by Master on-die wiring after the Master output buffer." This should be corrected in the model code.
- POR is similar. There is only one input buffer (Master) or output buffer (Slave). "For Masters, the two por bumps should be connected by Master on-die wiring before the Master input buffer."
"For Slaves, the two por bumps should be connected by Slave on-die wiring after the Slave output buffer." No ANDing or ORing should be done. This should also be corrected in the model code.
See figures 12 and 13 in the "AIB Usage Note" v1.2.
from aib-phy-hardware.
Check Commits on Dec 9, 2019 commit. This issue is closed by the RTL change.
from aib-phy-hardware.
Related Issues (20)
- Enhancement request: expose ns_mac_rdy downward from aib_top HOT 1
- Enhancement: for all channels expose the sideband shift registers HOT 1
- GDS for AIB bump locations? HOT 1
- Latency mismatch with AIB specification HOT 1
- Enhancement request: Support for emulation/FPGA HOT 3
- Warning SIOB on the model HOT 1
- Connection issue when change the DATA_WIDTH on SDR mode HOT 1
- MAC/PHY signal ns_mac_rdy is not connected from MAC through to the AIB bump HOT 1
- Warning select out of bound on the model HOT 1
- Connection issue HOT 2
- Dependencies of sideband on *adapter_rstn HOT 3
- Sideband RTL defaults don't seem to match AIB Spec tables HOT 1
- Need to identify where hardened synchronizer flops should be entered HOT 1
- por circuit in AIB Usage Note does not work HOT 1
- AIB 1.2 spec is missing Alternate (Slave) Channel Bump Map HOT 1
- Bump spreadsheet is missing Slave interface locations HOT 1
- Typos in AIB specification 1.2 HOT 1
- synthesis HOT 2
- mismatch between spec and model code. HOT 3
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