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GNSS Signal Generator writen on Verilog HDL for SDR platform (currently BladeRF)
Verilog 43.41%
SystemVerilog 56.59%
gnss-verilog-signal-simulator's Introduction
GNSS Verilog Signal Simulator
GNSS Signal Generator writen by Verilog.
This Signal Simulator generate signal as IF signal for SDR-backend (e.g. BladeRF).
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Written in SystemVerilog, and fully synthesisable
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Repetitive interrupt mode, Programmed to provide 3 different interval interrupt requests
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