FPGA FAST image feature detector implementation in VHDL.

Created by the PUT Vision Lab.

You are free to use the code for research/hobby purposes. If you plan to use the code or its fragments in a commercial application, please contact the Authors, so that further agreements can be made. If the posted code is useful to you, the Authors would be really grateful if you cite the folowing articles:

System on chip coprocessors for high speed image feature detection and matching M. Kraft, M. Fularz, A. Kasinski Prof. of Int. Conf. on Advances Concepts for Intelligent Vision Systems, Lecture Notes in Computer Science Vol. 6915, pp. 599-610

@inproceedings{ACIVS2011, author = {Marek Kraft and Michal Fularz and Andrzej Kasinski}, title = {System on Chip Coprocessors for High Speed Image Feature Detection and Matching}, booktitle = {Proceedings of the 13th International Conference on Advanced Concepts for Intelligent Vision Systems}, series = {ACIVS'11}, year = {2011}, isbn = {978-3-642-23686-0}, location = {Ghent, Belgium}, pages = {599--610}, publisher = {Springer-Verlag}, }

High-speed image feature detection using FPGA implementation of FAST algorithm M. Kraft, A. Schmidt, A. Kasinski Proc. of International Conference on Computer Vision Theory and Applications VISAPP 2008, vol. 1, pp. 174-179

@inproceedings{VISAPP2008, author = {Marek Kraft and Adam Schmidt and Andrzej Kasinski}, booktitle = {VISAPP (1)}, date = {2008-04-07}, editor = {Ranchordas, Alpesh and Araújo, Helder}, isbn = {978-989-8111-21-0}, pages = {174-179}, publisher = {INSTICC - Institute for Systems and Technologies of Information, Control and Communication}, title = {High-Speed Image Feature Detection Using FPGA Implementation of Fast Algorithm.}, year = 2008 }