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riscv-newlib

RISC-V port of newlib

riscv-opcodes

RISC-V Opcodes

riscv-openocd

Fork of OpenOCD that has RISC-V microcontroller support

riscv-profiles

RISC-V Architecture Profiles

riscv-software-list

The RISC-V software tools list, as seen on riscv.org

riscv-starship

Run rocket-chip on FPGA

riscv-trace-spec

Working Draft of the RISC-V Processor Trace Specification

riscv-v-spec

Working draft of the proposed RISC-V V vector extension

riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

riscvv

an open source uvm verification platform for e200 (riscv)

rocket-chip

Rocket Chip Generator

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

rv_plic

Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC). DEPRECATED in favour of the OpenTitan PLIC: https://github.com/lowRISC/opentitan/tree/master/hw/ip/rv_plic

schoolmips

CPU microarchitecture, step by step

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

sdram-verification

This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed by Dinesh in Opencores.org

shadowsocketstools_all

simple_soc

Small and simple, primitive SoC with GPU, CPU, RAM, GPIO

sm3_core

soc-dv

System on Chip verified with UVM/OSVVM/FV

soc-freedom-sifive

e300 and u500 devkits

soc-riscv

System on Chip with RISCV-32 / RISCV-64 / RISCV-128

soc_automation

SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.

srcery-vim

Dark colorscheme for gvim and vim

surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

sv-parser

SystemVerilog parser library fully complient with IEEE 1800-2017

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

svaunit

SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)

svaunit_sandbox

Example code for "A Quick Look at SVAunit" post

svlib

svlib from http://www.verilab.com/resources/svlib/