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usb2_dev

USB 2.0 Device IP Core

usb3_pipe

USB3 PIPE interface for Xilinx 7-Series

uvm

UVM examples and projects

uvm-1

Universal Verification Methodology (UVM) base libraries, with edits for Verilator

uvm-2

uvm-components

Contains commonly used UVM components (agents, environments and tests).

uvm-extras

Extensions to the UVM

uvm-python

UVM 1.2 port to Python

uvm-related-topics

uvm-tutorial-for-candy-lovers

Source code repo for UVM Tutorial for Candy Lovers

uvm_candy_lover

:candy:UVM candy lover testbench which uses YASA as simulation script

uvm_reg_to_ipxact

uvm_uart_example

An UVM example of UART

uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

ventus-gpgpu

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

verification-gentleman-blog-code

Example code for Verification Gentleman blog

verigpu

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

verilator

Verilator open-source SystemVerilog simulator and lint system

verilog-axi

Verilog AXI components for FPGA implementation

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-i2c

Verilog I2C interface for FPGA implementation

verilog-pcie

Verilog PCI express components

verilog-uart

Verilog UART

verilog-wishbone

Verilog wishbone components

verilogpp

vexriscv

A FPGA friendly 32 bit RISC-V CPU implementation

vgm_abstract_registry

UVM extension to support registering abstract classes with the factory

vgm_risc_v-e

RISC-V ISA model