@proppy

Expected Behavior

The verilog model should only use language constructs supported by the tool chain, i.e. only compiler directives implemented in the synthesis tool yosys.

Actual Behavior

The current verilog module uses the compiler directive `suppress_faults that is not implemented in yosys.
In consequence, when loading the verilog model into yosys, i.e. via the openlane variable VERILOG_FILES_BLACKBOX,
yosys will stop with error:

5. Executing Verilog-2005 frontend:

/content/eda/share/pdk/gf180mcuC/libs.ref/gf180mcu_fd_io/verilog/gf180mcu_fd_io.v
/content/eda/share/pdk/gf180mcuC/libs.ref/gf180mcu_fd_io/verilog/gf180mcu_fd_io.v:17: ERROR: Unimplemented compiler directive or undefined macro `suppress_faults.
child process exited abnormally

Steps to Reproduce the Problem

1. within config.tcl,

set ::env(VERILOG_FILES_BLACKBOX)   /content/eda/share/pdk/gf180mcuC/libs.ref/gf180mcu_fd_io/verilog/gf180mcu_fd_io.v

2. run flow.tcl -to synthesis

Specifications

• Version: yosys 0.26+53
• Platform: colab using https://github.com/proppy/conda-eda/releases/download/v0.0-1452-g75fd8b9/digital.gf180mcuc-0-Linux-x86_64.sh

Expected Behavior

Add the correct site definition "GF_IO_Site" and "GF_COR_Site" to the current *.lef file of the gf180mcu I/O library. The Site must be defined before it can be referenced within the pad cells.

The padd class need also be modified to AREAIO for each pad cell.

Actual Behavior

The current *.lef file of the I/O library does not contain the Site definition "GF_IO_SITE" and "GF_COR_Site"and therefor automatic IO cell placement does not work correctly.

Steps to Reproduce the Problem

See the attached patch file to see all required modifications

/cc @proppy
/cc @chaufe
gf180mcu_fd_io.lef.patch

Expected Behavior

all the variants of a given cell's .lef have unique MACRO names and can be concatenated by open_pdks in a single file.

Actual Behavior

variants have the same MACRO name, ex:

• https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_io/blob/main/cells/asig_5p0/gf180mcu_fd_io__asig_5p0_3lm.lef#L15
• https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_io/blob/main/cells/asig_5p0/gf180mcu_fd_io__asig_5p0_4lm.lef#L15

Expected Behavior

when the gf180mcu_fd_io__bi_t.cdl is run on ngspice by making the necessary connections of the pins to configure it to IE mode and drive a PULSE signal on PAD and plot output on Y port - the digital signals driven on PAD must show up on 'Y'

Actual Behavior

certain devices are not found in ngspice libs - and their symbols (example pfet_06v0_dss,nfet_06v0_dss) are not available in ngspice

Steps to Reproduce the Problem

take gf180mcu_fd_io__bi_t.cdl file in this repo and run on ngspice. Ngspice sims should run and you should be able to run digital signals on the PAD and plot the same on Y, A outputs (depending on digital pad configuration) as per -

Specifications

• Platform: proppy/conda

DRC violations in GF018green_ipio_5p0c_75_3lm vs. documented rule in the design manual

DF.1a

DF.14

This produces an error in reading the liberties for timing analysis. The duplicate definitions could be found in all liberties starting at lines 2906 and 2929
For example:

gf180mcuC/libs.ref/gf180mcu_fd_io/liberty/gf180mcu_fd_io__ff_n40C_5v50.lib
2906:	cell ("gf180mcu_fd_io__fill10") {
2929:	cell ("gf180mcu_fd_io__fill10") {

The reason probably is that the cell has a definition cell ("gf180mcu_fd_io__fill10") inside the file cells/fill1/gf180mcu_fd_io__fill10__ff_n40C_5v50.lib and cells/fill10/gf180mcu_fd_io__fill10__ff_n40C_5v50.lib