fusesoc / blinky Goto Github PK
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License: MIT License
Example LED blinking project for your FPGA dev board of choice
License: MIT License
When experimenting with the core before add another board I got the folowing error:
Unknown item 'filesets_append in section Target'
Fusesoc version: 1.9.2
I've been following these instructions and installed yosys
manually using apt
(apt install yosys -y
) but get this when trying to build the project:
neil@NEIL-LEGION:~$ fusesoc run --target=tang_nano fusesoc:utils:blinky
WARNING: Unknown item board_device_index in section Ise
INFO: Preparing fusesoc:utils:blinky:1.1.1
INFO: Setting up project
INFO: Setting up project
INFO: Setting up project
INFO: Building
yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl'
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2019 Clifford Wolf <[email protected]> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9 (git sha1 1979e0b)
-- Running command `tcl edalize_yosys_template.tcl' --
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
1. Executing Verilog-2005 frontend: ../src/fusesoc_utils_blinky_1.1.1/tang_nano/blinky.v
Parsing Verilog input from `../src/fusesoc_utils_blinky_1.1.1/tang_nano/blinky.v' to AST representation.
Storing AST representation for module `$abstract\top'.
Successfully finished Verilog frontend.
Syntax error in command `synth_gowin -json fusesoc_utils_blinky_1.1.1.json -top top':
synth_gowin [options]
This command runs synthesis for Gowin FPGAs. This work is experimental.
-top <module>
use the specified module as top module (default='top')
-vout <file>
write the design to the specified Verilog netlist file. writing of an
output file is omitted if this parameter is not specified.
-run <from_label>:<to_label>
only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.
-nodffe
do not use flipflops with CE in output netlist
-nobram
do not use BRAM cells in output netlist
-nodram
do not use distributed RAM cells in output netlist
-noflatten
do not flatten design before synthesis
-retime
run 'abc' with -dff option
The following commands are executed by this synthesis command:
begin:
read_verilog -lib +/gowin/cells_sim.v
hierarchy -check -top <top>
flatten: (unless -noflatten)
proc
flatten
tribuf -logic
deminout
coarse:
synth -run coarse
bram: (skip if -nobram)
memory_bram -rules +/gowin/bram.txt
techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v
dram: (skip if -nodram)
memory_bram -rules +/gowin/dram.txt
techmap -map +/gowin/drams_map.v
determine_init
fine:
opt -fast -mux_undef -undriven -fine
memory_map
opt -undriven -fine
techmap -map +/techmap.v -map +/gowin/arith_map.v
techmap -map +/techmap.v
abc -dff (only if -retime)
map_ffs:
dffsr2dff
dff2dffs
opt_clean
dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*
techmap -map +/gowin/cells_map.v
opt_expr -mux_undef
simplemap
map_luts:
abc -lut 4
clean
map_cells:
techmap -map +/gowin/cells_map.v
hilomap -hicell VCC V -locell GND G
iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O (unless -noiopads)
dffinit -ff DFF Q INIT
clean
check:
hierarchy -check
stat
check -noinit
vout:
write_verilog -nodec -attr2comment -defparam -renameprefix gen <file-name>
ERROR: Command syntax error: Unknown option or option in arguments.
> synth_gowin -json fusesoc_utils_blinky_1.1.1.json -top top
> ^
make: *** [Makefile:6: fusesoc_utils_blinky_1.1.1.json] Error 1
ERROR: Failed to build fusesoc:utils:blinky:1.1.1 : '['make']' exited with an error: 2
neil@NEIL-LEGION:~$
In looking into this, the yosys
version installed by Aptitude on Ubuntu 20.04 (WSL on Windows 10) doesn't support the -json
flag:
neil@NEIL-LEGION:~$ yosys -V
Yosys 0.9 (git sha1 1979e0b)
neil@NEIL-LEGION:~$ yosys --help
Usage: yosys [options] [<infile> [..]]
-Q
suppress printing of banner (copyright, disclaimer, version)
-T
suppress printing of footer (log hash, version, timing statistics)
-q
quiet operation. only write warnings and error messages to console
use this option twice to also quiet warning messages
-v <level>
print log headers up to level <level> to the console. (this
implies -q for everything except the 'End of script.' message.)
-t
annotate all log messages with a time stamp
-d
print more detailed timing stats at exit
-l logfile
write log messages to the specified file
-L logfile
like -l but open log file in line buffered mode
-o outfile
write the design to the specified file on exit
-b backend
use this backend for the output file specified on the command line
-f frontend
use the specified frontend for the input files on the command line
-H
print the command list
-h command
print the help message for the specified command
-s scriptfile
execute the commands in the script file
-c tcl_scriptfile
execute the commands in the tcl script file (see 'help tcl' for details)
-p command
execute the commands
-m module_file
load the specified module (aka plugin)
-X
enable tracing of core data structure changes. for debugging
-M
will slightly randomize allocated pointer addresses. for debugging
-A
will call abort() at the end of the script. for debugging
-D <macro>[=<value>]
set the specified Verilog define (via "read -define")
-P <header_id>[:<filename>]
dump the design when printing the specified log header to a file.
yosys_dump_<header_id>.il is used as filename if none is specified.
Use 'ALL' as <header_id> to dump at every header.
-W regex
print a warning for all log messages matching the regex.
-w regex
if a warning message matches the regex, it is printed as regular
message instead.
-e regex
if a warning message matches the regex, it is printed as error
message instead and the tool terminates with a nonzero return code.
-E <depsfile>
write a Makefile dependencies file with in- and output file names
-g
globally enable debug log messages
-V
print version information and exit
The option -S is an shortcut for calling the "synth" command, a default
script for transforming the Verilog input to a gate-level netlist. For example:
yosys -o output.blif -S input.v
For more complex synthesis jobs it is recommended to use the read_* and write_*
commands in a script file instead of specifying input and output files on the
command line.
When no commands, script files or input files are specified on the command
line, yosys automatically enters the interactive command mode. Use the 'help'
command to get information on the individual commands.
neil@NEIL-LEGION:~$
I'm completely new to FPGA development and the associated toolchains, so could someone please help me figure out how I can build the project in my environment? Thanks!
I am trying to run the simple blinky example and I keep getting the following error:
ERROR: 'fusesoc:utils:blinky' or any of its dependencies requires 'blinky', but this core was not found
What I did was the following:
git clone https://github.com/fusesoc/blinky.git
cd blinky/
fusesoc run --target=sim fusesoc:utils:blinky --help
I read the documentation and some issues in this repo. I also tried the following command and I still get the same error:
fusesoc core show fusesoc:utils:blinky
Is there anything that I am missing here?
According to the README:
This project is available in the FuseSoC base library, so if you have FuseSoC installed, you likely already have this project as well.
However, when I ran fusesoc list-cores
, blinky
wasn't included. I also couldn't find it here: https://github.com/fusesoc/fusesoc-cores.
Is the README wrong or hasn't it been included in the standard library just yet?
Tom
Hello,
I installed fusesoc with
pip3 install --upgrade --user fusesoc
checked the version with
fusesoc --version
which returned "2.3", made a new directory and executed
fusesoc library add blinky https://github.com/fusesoc/blinky
and tried to execute
fusesoc run --target=sim fusesoc:utils:blinky
but got following error message
ERROR: Conflicting requirements:
Requirements: 'fusesoc_utils_blinky == 1.1.1-0' <- 'vlog_tb_utils >= 0-0'
+fusesoc_utils_blinky-1.1.1-0 was ignored because it depends on missing packages
Requirements: 'fusesoc_utils_blinky == 1.1.1-0'
Install command rule (+fusesoc_utils_blinky-1.1.1-0)
Failed to resolve dependencies for fusesoc:utils:blinky:1.1.1
while executing
fusesoc core list
returns following
Available cores:
Core Cache status Description
================================================================================
fusesoc:utils:blinky:1.1.1 : local : <No description>
Did I made a mistake or what happened?
I integrated several armadeus boards in the blinky project.
These boards are all built with spartan fpga and use ISE toolchain for synthesis.
Constructing bitstream works well with fusesoc commands :
fusesoc run --target=opos6ul_sp fusesoc:utils:blinky
But end with impact error configurator :
Cable connection failed.
Cable autodetection failed.
ERROR: Failed to run fusesoc:utils:blinky:1.0 : 'impact' exited with an error code
I can't configure armadeus board FPGA with impact, to configure it I have to download bitstream in uboot and launch config command on board.
Then, Is there an option to says : hey do not try to configure the FPGA ?
And get no error.
I tried the LED to believe tutorial in https://github.com/fusesoc/blinky for a Sipeed Tang Nano board with a fresh install of FuseSoc, Yosys, and Apicula with Python 3.9.5 on Linux Mint x86_64.
After running fusesoc core list
and finding a core called fusesoc:utils:blinky
in the list, I tried to build the project with:
fusesoc run --target=tang_nano fusesoc:utils:blinky
This produced an error message that wasn't helpful to me as someone just getting started with FuseSoC:
ERROR: No tool was supplied on command line or found in 'fusesoc:utils:blinky' core description
I carefully re-checked my installation and ran fusesoc library update
as instructed just in case, even though a brand new installation should have been (and was) up to date, but the error persisted. Finally after looking through the repositories and reading the various files, I eventually discovered that there was a tang_nano
target in https://github.com/fusesoc/blinky/blob/master/blinky.core that was not present in https://github.com/fusesoc/fusesoc-cores/blob/master/fusesoc_utils/blinky-1.0.core.
The instructions said to install blinky
as a new core library, with the command fusesoc library add blinky https://github.com/fusesoc/blinky
, "If it's still not there, or if you want to modify the project, e.g. to add support for an additional board," none of which applied in my case. But after running this command (and addressing a separate issue with Edalize) I was able to build and run blinky
.
This could be a lot more pleasant for someone just getting started with FuseSoC. Is there a reason why the two blinky
cores are not identical, or in any case don't support the same range of targets? If so, could there be clearer instructions for users with boards that require use of the stand-alone blinky
core?
**Brief introduction of the Arrow Chameleon96 board (https://www.96boards.org/product/chameleon96/):
This board is a Cyclone V board (same chip as de10-nano) but FPGA was considered secondary and Novtech who designed the board did not include a direct pin clock into the FPGA fabric...
So in this board to get a clock signal we must use Platform Designer (Qsys) and loan one of the HPS clocks (ARM side) to the FPGA side (This is what Altera call LoanIO pins).
**What is needed to port Fusesoc cores to Chameleon96:
Firstly I need to include a .qsys file but I think this is not suported in Fusesoc yet. I tried with this but gave me error of course because it's not a verilog file.
Hi!
I wanted to try out fusesoc (since I heard so many great things about it) and got stuck at running blinky :(
I have a PYNQ_Z1 board and it is basically the same as PYNQ_Z2 that is supported already in the blinky project. For some reason, when i try to run it with
$ fusesoc run --target=pynq_z2 fusesoc:utils:blinky
I get
ERROR: No tool was supplied on command line or found in 'fusesoc:utils:blinky' core description
which is weird since PYNQ_Z2 has default_tool defined to vivado.
Then I added the --tool=vivado
option
$ fusesoc run --tool=vivado --target=pynq_z2 fusesoc:utils:blinky
but I got another error
ERROR: Failed to determine work root. Could not resolve target
Could you please help me.
Hi there,
I am trying to support the blinky example in an Alhambra board. For that I have added a pcf file and the board support in the blinky.core file (here and here), following the tinyfpga_bx
as example.
In order to load it in fusesoc
this repo, I have used fusesoc library add blinky /path/to/repo
command.
I am able to synth the example using fusesoc run --target=alhambra_II fusesoc:utils:blinky
command.
The issue is that, once I upload the bin file, it doesn't blink. I have checked the clk
input pin and it is fine. The LED I have assigned, once the FPGA is programmed, goes from high-impedance to OFF.
Am I missing something?
I'd like to add a Verilog simulation to the blinky project, mainly as I prefer to use Verilator over Icarus. Is there an example project I can look at to do this?
Hi,
In the step,
To build for your particular board, run fusesoc run --target= fusesoc:utils:blinky where is one of the boards listed in the Board support section below.
If I'm adding a new board, what should the target be specified as? From earlier in the documentation I am assuming support for new boards are allowed to be added as well. I'm working with a Nexys Video btw.
Thanks!
B:\fuse>fusesoc run --target=nexys_a7 fusesoc:utils:blinky
←[1;37mINFO: Preparing fusesoc:utils:blinky:0←[0m
Traceback (most recent call last):
File "c:\python37\lib\runpy.py", line 193, in _run_module_as_main
"main", mod_spec)
File "c:\python37\lib\runpy.py", line 85, in run_code
exec(code, run_globals)
File "C:\Python37\Scripts\fusesoc.exe_main.py", line 9, in
File "c:\python37\lib\site-packages\fusesoc\main.py", line 604, in main
args.func(cm, args)
File "c:\python37\lib\site-packages\fusesoc\main.py", line 262, in run
flags, args.system_name, args.system, args.backendargs, args.build_root)
File "c:\python37\lib\site-packages\fusesoc\main.py", line 339, in run_backend
backend.configure(backendargs)
File "c:\python37\lib\site-packages\edalize\edatool.py", line 103, in configure
self.configure_main()
File "c:\python37\lib\site-packages\edalize\vivado.py", line 70, in configure_main
template_vars)
File "c:\python37\lib\site-packages\edalize\edatool.py", line 237, in render_template
template = self.jinja_env.get_template(os.path.join(template_dir, template_file))
File "c:\python37\lib\site-packages\jinja2\environment.py", line 830, in get_template
return self._load_template(name, self.make_globals(globals))
File "c:\python37\lib\site-packages\jinja2\environment.py", line 804, in _load_template
template = self.loader.load(self, name, globals)
File "c:\python37\lib\site-packages\jinja2\loaders.py", line 113, in load
source, filename, uptodate = self.get_source(environment, name)
File "c:\python37\lib\site-packages\jinja2\loaders.py", line 232, in get_source
pieces = split_template_path(template)
File "c:\python37\lib\site-packages\jinja2\loaders.py", line 31, in split_template_path
raise TemplateNotFound(template)
jinja2.exceptions.TemplateNotFound: vivado\vivado-project.tcl.j2
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