Possible problem with DCACHE when using VexRiscv about litex HOT 6 CLOSED

Thanks, i'll try to reproduce. Do you have a minimal firmware to load with flterm that trigger the issue? (On others project we are running software from DDR with VexRiscv, so that would help understand what is going on).

from litex.

Yes, I know this looks suspicious.

I've prepared a minimal test for that:
https://github.com/pgielda/litex-baremetal-test

This is a very minimal standalone baremetal program. The only trick there is that I "steal" flush_cpu_dcache so you will need to update the address in linker.ld with a correct one.

Just tested this and it only works if the flush_cpu_dcache is called 3 times at the beginning. Otherwise the firmware reboots the board (which means that mcause was != 0).

If you do not want to update linker.ld you can also remove flush_cpu_dcache calls from my code, test and prove that the code reboots itself, then add those to boot.c in the BIOS and see that the code stops rebooting.

At least this happens on my setup with ARTY.

from litex.

It seems flushing dcache and l2_cache make it work, can you test with upstream LiteX?

from litex.

Thanks, this change looks promising. I will test this over the weekend.

from litex.

OK thanks.

from litex.

I can confirm that his fixes the problem.

from litex.