How to drive `soc_rst` from an external pin? about litex HOT 4 CLOSED

class CRG(Module, AutoCSR):
    """Clock and Reset Generation"""

    def __init__(self, platform):
        self.rst = Signal()
        self.clock_domains.cd_sys = ClockDomain()
        self.clock_domains.cd_por = ClockDomain(reset_less=True)
        self.clock_domains.cd_ext = ClockDomain()

        clk_in = platform.request(platform.default_clk_name)
        clk_in_freq = round(1e9 / platform.default_clk_period)

        # Power on reset
        por_count = Signal(16, reset=2**16 - 1)
        por_done = Signal()
        self.comb += self.cd_por.clk.eq(clk_in)
        self.comb += por_done.eq(por_count == 0)
        self.sync.por += If(~por_done, por_count.eq(por_count - 1))

        # PLL
        self.submodules.pll = pll = ECP5PLL()
        self.comb += pll.reset.eq(~por_done | self.rst)
        pll.register_clkin(clk_in, clk_in_freq)
        pll.create_clkout(self.cd_sys, 50e6, margin=0, with_reset=False)

        # The SYS domain is reset whenever the PLL is unlocked
        sys_rst = Signal()
        self.comb += sys_rst.eq(~pll.locked)
        self.specials += AsyncResetSynchronizer(self.cd_sys, sys_rst)

        # External push button reset synchronised into its own domain
        rst_n = platform.request("rst_n")
        self.comb += self.cd_ext.clk.eq(self.cd_sys.clk)
        self.specials += AsyncResetSynchronizer(self.cd_ext, ~rst_n)


class VersaSoC(SoCCore):
    """Top level of the Versa platform"""

    def __init__(self, **kwargs):
        platform = lattice_versa_ecp5.Platform(device="LFE5UM", toolchain="trellis")
        SoCCore.__init__(self, platform=platform, clk_freq=50e6, **kwargs)

        # Clock/Reset Generator
        self.crg = CRG(platform)

        # Hook up the push button reset
        self.comb += If(self.crg.cd_ext.rst, self.cpu.reset.eq(1))

        # Hook up the push button reset
        self.comb += self.cpu.reset.eq(self.cpu.reset | ~self.crg.rst_n)