Comments (2)
Conversely, I am using WSL2 for Litex builds and have Gowin IDE installed in Windows natively, with my PATH pointing to the native bin folder. The EXE check is needed for my setup to work.
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Conversely, I am using WSL2 for Litex builds and have Gowin IDE installed in Windows natively, with my PATH pointing to the native bin folder. The EXE check is needed for my setup to work.
Does WSL2 allow interfacing with windows installed Gowin? I tried this and it gets
Cannot open Verilog file 'C:\mnt\c\fpga\litex\litex_demo\build\top.v'
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Related Issues (20)
- Support of RapidIO
- Support of Interlaken protocol
- Support of IO-Link
- Support of MIPS cores
- Generated DTS lacks root compatible and model properties HOT 3
- Restrict bus crossbar access by region mode
- Add example for embedding a LiteX SOC into Vivado project for Zynq HOT 4
- litex_sim of CV32E41P is stuck HOT 2
- Liteeth: Broken constraints HOT 4
- UART output not displayed HOT 2
- Can't boot linux with MAIN_RAM sizes above 512mb HOT 68
- liteeth linux driver performances HOT 6
- How to set multi-level sequential trigger in litescope ? HOT 1
- Native windows Vivado and WSL2 Litex build fails to find toolchain HOT 2
- default FIFO depth for video is too large for some devices
- Loading binary hangs up HOT 3
- Weird builder args behaviour
- Trying to interact with UART via Rust binary (stuck at liftoff) HOT 2
- RISC-V debug module support for CV32E40P/41P ?
- Issues with main memory > 1GB HOT 1
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