Add example for embedding a LiteX SOC into Vivado project for Zynq about litex HOT 4 OPEN

If I correctly understood your attempt you wish to use the ARM processor (PS) as a master and adding some cores, connected to the AXI (cores acting as slave, PS as master). Is it true?

If so: why not using

./yourBoard.py --cpu-type zynq7000 [...]

This is working on most of the Zynq based board supported by LiteX (see digilent_zedboard.py or digilent_arty_z7.py).

If your target board hasn't been already tested/validated in this use case (as xilinx_zc706.py you have to update target file with parts specifics to zynq7000 support (again see digilent_zedboard.py as example).

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I have check some zynq boards. Some zynq board use a xci file for hard zynq core (like redpitaya) , some use preset (not every board has preset) or tcl config (only see arty_z7). I am not fimilar with these methods, and not confident to generate a working PS core. I try use a self make xci, for some reason not working.

In the example I show, I can change PS ip using "Customize Block GUI" any time after genrate liteX soc.

I can then develop apps using Vitis or petalinux (in theory, haven't tried), which provide easy enviremnet for build and debugging. I understand that liteX in flavor, software build can be intergrated in Python work flow. But for beginners like me, an IDE with some template projects will get me start very quickly.

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Hi @benfre,

thanks for the feedback and detailed explanations. This indeed is a nice way to integrate things and could be convenients for users familiar with Vivado Block Design. We are also using a similar approach to package/integrate different cores (ex LiteDRAM, LitePCIe, LiteEth, etc...) for users also using Vivado Block Design.

I'll have a closer look a it and if you are OK with it, this could probably be a nice tutorial to be included in the wiki!

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I'm OK with this.

I'll have a closer look a it and if you are OK with it, this could probably be a nice tutorial to be included in the wiki!

Please have a closer look. I'm not familiar with migen or LiteX. This example take me couples of weeks to get working. The only AXI-lite interface and address width issue can have some fixes.

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