Liteeth: Broken constraints about litex HOT 4 OPEN

Nvm, I'm wrong with what I said above. Exactly the same timing issues are present in the multicore VexRiscv image, and there ethernet works. In as far as the sdcard is concerned, I found out that it only works for 100 MHz or 50 MHz, but not for 75 Mhz, is this intended? But regarding ethernet, I'm still dumbfounded. Maybe it's a driver issue. I'll investigate further.

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Ok, it is definitely related to recent crc changes in liteeth. I could reproduce the issue with latest liteeth on VexRiscv. Liteeth release tag 2023.12 works perfectly fine tough, tested with VexRiscv and NaxRiscv SoCs. Finally I can connect to the internet via Debian on quad core NaxRiscv! :)

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Hi @tristantschner,

would you mind sharing your build command? I'll have a look at the timing issue and compare upstream with 2023.12.

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The command was:

python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=naxriscv --bus-standard axi-lite \
--with-video-framebuffer --with-coherent-dma --with-spi-sdcard --with-ethernet --xlen=64 \
--scala-args='rvc=true,rvf=true,rvd=true,alu-count=2,decode-count=2' --with-jtag-tap \
--sys-clk-freq 75000000 --cpu-count 4 --soc-json build/digilent_nexys_video/csr.json \
--update-repo no --build

I used Vivado version 2023.2. I also still have the implemented design check point on my disk, if you'd like that.

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