IOStandard missing for Efinix PLL clock reference about litex HOT 2 OPEN

Hi,
Efinix is a bit different to any others FPGA's vendors. Some of primitives (including PLL) are out of verilog and managed by the interface designer.
In this specific case the input clock isn't something at verilog top level but it's used directly by the PLL.
If you check build/yourBoard/gateware/iface.py you may found a line like:

design.gen_pll_ref_clock("pll0", pll_res="PLL_TL0", refclk_src="EXTERNAL", refclk_name="clk25", ext_refclk_no="0")

refclk_name isn't really relevant but ext_refclk_no inform about which PLL's input is used.

Which is your board? To check this behaviour.
Thanks

from litex.

I'm using a custom Ti180 board that has 3.3V oscillators. When the peri.xml file is created for the Efinity project, the property to set the IO standard would not get created causing a mismatch between the clock and the bank voltages.

design.set_property("clk","IO_STANDARD","1.8_V_LVCMOS")

from litex.