Hi Bruno, simply execute the makeit.sh and it report fail, here is the output, it seems strange.

ubuntu@ubuntu:~/oss/learn-fpga/FemtoRV/TEST$ ./makeit.sh
./femtorv32.v:773: syntax error
./femtorv32.v:767: error: syntax error in parameter value assignment list.
./femtorv32.v:767: error: Invalid module instantiation
./femtosoc.v:112: error: NULL port declarations are not allowed.
./femtosoc.v:681: syntax error
./femtosoc.v:669: error: Syntax error in instance port expression(s).
bench: Unable to open input file.

I can compile LiteOS for the quark variant just fine, but when I try petitbateau variant, I get this error:

CC       boot.elf
/home/farmer/litex/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/../lib/gcc/riscv64-unknown-elf/8.1.0/../../../../riscv64-unknown-elf/bin/ld: /home/farmer/litex/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/../lib/gcc/riscv64-unknown-elf/8.1.0/libgcc.a(div.o): ABI is incompatible with that of the selected emulation:
  target emulation `elf64-littleriscv' does not match `elf32-littleriscv'
/home/farmer/litex/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/../lib/gcc/riscv64-unknown-elf/8.1.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /home/farmer/litex/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/../lib/gcc/riscv64-unknown-elf/8.1.0/libgcc.a(div.o)
collect2: error: ld returned 1 exit status
Makefile:21: recipe for target 'boot.elf' failed

Dear Bruno,

my congratulations for squeezing a RV32I core into the Icestick !

I read your Verilog files with joy and I wish to share an idea on how to save a few more LUTs for more peripherals: Try an "one-hot" IO address decoder. You have few IO registers only, so you can reserve one address line for each of your peripheral registers and save LUTs on comparisons with the full IO address. This also allows to set multiple IO registers at once.

You can also insert a hardware random number generator by using a ring oscillator.

Maybe you wish to check out Mecrisp-Ice from mecrisp.sourceforge.net in file mecrisp-ice-1.8/hx1k/icestorm/j1a.v for my peripheral set in use on the Icestick. Mecrisp-Ice is a Forth compiler running on a stack processor, which is a descendant of Swapforth and the J1a CPU by James Bowman. I think you can borrow a few of the ideas !

If you manage to map the SPI flash into the memory bus within the available LUTs, similiar to the memory interface in Picosoc, I would be happy to officially port Mecrisp-Quintus (a RISC-V Forth which needs about 24kb flash and 4 kb RAM) to your FemtoRV32 on the Icestick.

Hats off and best wishes from Germany,
Matthias

PS: Completely removing the rdRAM wire in your memory design somehow saved 20 LUTs.

Yesterday's work raised some PLL related issues for up5k document these in the ice40 markdown page instead of scattered in twitter / PR. Also capture the essence of add new board with exact path I took to get build working.

Dear Bruno,

Seems there is an unexpected semicolon when running "make ICESTICK" from FemtoRV example as seen below :

RTL/DEVICES/MappedSPIFlash.v:306: ERROR: syntax error, unexpected ';'

/*********************************/

function [15:0] bbyyttee;
input [7:0] x;
begin
bbyyttee = {
x[7],x[7],x[6],x[6],x[5],x[5],x[4],x[4],
x[3],x[3],x[2],x[2],x[1],x[1],x[0],x[0]
};
end
endfunction; <-- here

/********************************/
Kind regards
KiranKanchi

I was following FROM_BLINKER_TO_RISCV tutorial on a ULX3S, and it all started great but when trying to run step 17 on the board it says:

BOARDS/run_ulx3s.sh step17.v

step17.v:455: ERROR: Unimplemented compiler directive or undefined macro `CPU_FREQ.

I checked and indeed BOARDS/run_ulx3s.sh doesn't have CPU_FREQ defined while BOARDS/run_icestick.sh has it.

I tried defining it with some values, but then more issues appeared which I'm not sure how to solve:

ERROR: Module \femtoPLL' referenced in module \Clockworks' in cell `\genblk1.pll' is not part of the design.

Any help would be great.

Hello! We are having Issue with using milliseconds. upon even referencing the function in any part of code makes the CPU stop executing the code. We are using icebreaker board config file, We managed to make work on iCE40 Ultraplus breakout board.

we have enabled peripherals : SD card, QUARK cpu, LED driver and UART.

Here is board config file :

// Default femtosoc configuration file for IceStick

`define NRV_NEGATIVE_RESET
/************************* Devices **********************************************************************************/

`define NRV_IO_LEDS      // Mapped IO, LEDs D1,D2,D3,D4 (D5 is used to display errors)
`define NRV_IO_UART      // Mapped IO, virtual UART (USB)
//`define NRV_IO_SSD1351   // Mapped IO, 128x128x64K OLed screen
//`define NRV_IO_MAX7219   // Mapped IO, 8x8 led matrix
`define NRV_IO_SDCARD 
`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space. Can be used with MINIRV32 to run code from SPI flash.

/************************* Processor configuration ******************************************************************/

//`define NRV_FEMTORV32_ELECTRON      // RV32IM
//`define NRV_FEMTORV32_INTERMISSUM   // RV32IM  + IRQ
//`define NRV_FEMTORV32_GRACILIS      // RV32IMC + IRQ
//`define NRV_FEMTORV32_PETITBATEAU     // RV32IMFC + IRQ, does not fit on IceBreaker
`define NRV_FEMTORV32_QUARK

`define NRV_FREQ 20                 // Frequency in MHz. Recomm: 15 MHz   Overclocking: 20-25 MHz
`define NRV_RESET_ADDR 32'h00820000 // Jump execution to SPI Flash (800000h, +128k(20000h) for FPGA bitstream)
// tinyraytracer: 30 MHz RV32IM  electron 3:12
//                20 MHz RV32IM  gracilis 3:44
//                20 MHz RV32IMC gracilis 3:32
//                25 MHz RV32IMC gracilis 2:49

/************************* RAM (in bytes, needs to be a multiple of 4)***********************************************/

// Using the 128 kbytes of single-ported RAM of the ice40-up5k
// Note: cannot initialize it from .hex file, need to run from SPI Flash

`define ICE40UP5K_SPRAM
`define NRV_RAM 131072 

// (other option, the 12 kbytes of BRAM, this one can be initialized from .hex file).
//`define NRV_RAM 12288

/************************* Advanced devices configuration *********************************************************/

`define NRV_RUN_FROM_SPI_FLASH // Do not 'readmemh()' firmware from '.hex' file
`define NRV_IO_HARDWARE_CONFIG // Comment-out to disable hardware config registers mapped in IO-Space
                               // (only if you use your own firmware, libfemtorv32 depends on it)

/******************************************************************************************************************/

`define NRV_CONFIGURED

Would be good to

• make FemtoRV32 and the cores in RTL/DEVICES/ available through FuseSoc,
• use other FuseSoc cores in FemtoSoc

Hello Bruno,

I have the Winbond W25Q32JV FLASH now working in SPI_FLASH_FAST_READ_DUAL_IO mode. According to the data sheet, this FLASH does not need dummy cycles in Fast Read Dual I/O mode. Instead of 8 dummy cycles (two byte) it needs one single Mode byte, correspondent to 4 cycles. The mode bits 5 and 4 should not equal to 2'b10, since this would change the behavior of the next read command.

From MappedSPIFlash.v, line 295:

clock_cnt <= 5'd28; // cmd: 8 clocks address: 12 clocks dummy: 8 clocks

If I set clock_cnt to 5'd24, everything is fine with my board. I tested with 16 MHz and 66 MHz clock frequency.

Regards, Bernd.

Develop a SDRAM controler

1. a small standalone project with a framebuffer and HDMI
2. map it in the address space of FemtoRV32
3. FemtoRV32 full access (code + data)
   Links:
   SDRAM notes: https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/SDRAM.md
   HDMI notes: https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/HDMI.md
   Small HDMI project: https://github.com/BrunoLevy/learn-fpga/tree/master/Basic/ULX3S_hdmi

Adapt existing tutorials format for iCE40-Feather.

https://github.com/farahmandakbar/octicons/blob/main/LICENSE

In commit 3ab7eaa to master branch of LiteX, a flag was removed which causes our build to fail. It works on commits prior to that one. This is the error that is given when we try to run make.

ecamp@CB459-EE11772:~/Projects/litex/learn-fpga/LiteX/software/LiteOS$ make
 CC       complete.o
 CC       helpers.o
 CC       readline.o
 CC       cmd_bios.o
 CC       builtins.o
 CC       isr.o
 CC       main.o
 CC       crt0.o
 CC       lite_oled.o
../Libs/lite_oled.c: In function 'oled_init':
../Libs/lite_oled.c:10:8: warning: unused variable 'trigger_warning' [-Wunused-variable]
    int trigger_warning; // LiteX synthesized without OLED support (graphics commands will be ignored)
        ^~~~~~~~~~~~~~~
 CC       lite_fb.o
../Libs/lite_fb.c: In function 'fb_line':
../Libs/lite_fb.c:212:111: warning: 'y' may be used uninitialized in this function [-Wmaybe-uninitialized]
 #define code(x,y) ((x) < fb_clip_x1) | (((x) > fb_clip_x2)<<1) | (((y) < fb_clip_y1)<<2) | (((y) > fb_clip_y2)<<3)
                                                                                                               ^~
../Libs/lite_fb.c:221:11: note: 'y' was declared here
     int x,y,dx,dy,sx,sy;
           ^
../Libs/lite_fb.c:221:9: warning: 'x' may be used uninitialized in this function [-Wmaybe-uninitialized]
     int x,y,dx,dy,sx,sy;
         ^
 CC       lite_elf.o
 CC       lite_stdio.o
 CX       imgui.o
 CX       imgui_demo.o
 CX       imgui_draw.o
 CX       imgui_tables.o
 CX       imgui_widgets.o
 CX       imgui_sw.o
ar cq libliteos.a lite_oled.o lite_fb.o lite_elf.o lite_stdio.o imgui.o imgui_demo.o imgui_draw.o imgui_tables.o imgui_widgets.o imgui_sw.o 
ranlib libliteos.a
 CC       boot.elf
/home/ecamp/Projects/litex/litex/build/digilent_nexys_video/software/libbase/libbase.a(memtest.o): In function `csr_write_simple':
/home/ecamp/Projects/litex/litex/litex/soc/software/include/hw/common.h:33: undefined reference to `__muldi3'
/home/ecamp/Projects/litex/litex/build/digilent_nexys_video/software/libbase/libbase.a(memtest.o): In function `print_speed':
/home/ecamp/Projects/litex/litex/litex/soc/software/libbase/memtest.c:181: undefined reference to `__muldi3'
collect2: error: ld returned 1 exit status
make: *** [Makefile:21: boot.elf] Error 1

• Add notes on ice-feather experiments with PASSTHROUGH_PLL
• Add notes on firmware size minimization -Os
• Fix build issues
• Add full config block in femtosoc_config.v in the docs

After compiling and uploading the program using command make main.prog the output files of compiler is removed and We right now need them for debugging purpose. so how can we disable the auto remove function. I tried to comment out the line 168 of makefile.inc which seems to be removing but that didn't worked. any help will be appreciated.

Hi,

It looks like there is a missing include file:

$ cd learn-fpga/FemtoRV/FIRMWARE/LiteX/DemoBundle
$ make BUILD_DIR=/home/matt/litex_2022/build/radiona_ulx3s/
 CC       tinyraytracer.o
demos/tinyraytracer.c:6:10: fatal error: demos.h: No such file or directory
 #include "demos.h"
          ^~~~~~~~~
compilation terminated.
make: *** [Makefile:110: tinyraytracer.o] Error 1

I cannot see demos.h in the repos.....

Thanks,
Matt

Hi Bruno, I try to build these demos, but buid failed, I notice the gcc is riscv64-linux-gnu-gcc-10, which toolchain do you use?
I replace the toolchain with https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz
and it report failed with this error
sysdeps/riscv/sfp-machine.h:21:10: fatal error: fpu_control.h: No such file or directory

Hi,
I was following learn-fpga/FemtoRV/TUTORIALS/litex.md and it says:

determine SDRAM chip (see image): one of MT48LC16M16, AS4C32M16 or AS4C16M16

However, mine, like the majority of ULX3S has a IS42S16160G in them (see here at the bottom of the page)

Could these instructions be updated to state what value the SDRAM variable should be set to for this case?

Thanks,
Matt

How long it takes to synthetize the blink example with the open toolchain in the Arty 35T ?

I am thinking to include the toolchain in IceStudio, but it's worth it if takes few seconds to synthetize the bitstream

Thanks and regards

The iceFeather comes with a peripherals wing containing a 6x6 LED Matrix, An RGB LED and 4 buttons. There is also an on-board SPI Flash. Document some option enabling these.

I tried to run a simulation of femtorv32_quark.v using the Vivado simulator, because I my SoC gets past synthesis well, but gets minimized to nothing during implementation, I do not know what is going on.

So I noticed the memory bus address is x after reset is removed. This would not be a problem with Verilator, but in a 4-state simulator x is likely to be propagated through the design. In my case the CPU does not change state with clock.
I went looking at what is on the address bus at reset:
https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v#L217-L218
https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v#L335
And the state is initialized to WAIT_ALU_OR_MEM while state FETCH_INSTR sounds like the right choice to have PC on the address bus at reset.

So I made this change, without checking if there are any other non obvious expectations. Verilator simulations got the same results as before and in Vivado simulation the CPU actually started fetching instructions.

Could you please review this change with your insight and maybe modify similar issues in other implementations.

The morale of the story is, Verilator 2-state simulation can sometimes hide some issues, expecially if don't care values are often used in RTL. My RTL is full of them, so I have to simulate with --x-assign argument set to both 0 and 1.

Potentially interesting project: adding an interface so that the user can attach their own function unit(s) for handling instructions in the RISC-V CUSTOM0 / CUSTOM1 opcode space. For example, PicoRV32 has PCPI.

Add a new GPIO peripheral, with up to 32 pins, two registers, one (W) to configure direction, and one (RW) to read/write values.

1. fully implement instructions to manipulate the CSRs
2. two levels of privilege, ECALL and EBREAK, implement FEMTOS syscalls, SDCard file access and terminal.
3. three levels of privilege
4. MMU
5. run Linux
   Links:
   https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/priviledged.md

Implement RV32F / RV32D instructions.
Take a look at FloPoCo
Links:
https://tel.archives-ouvertes.fr/tel-00654121v2/document

Hello Bruno,

there might be a problem in the SPI_FLASH_FAST_READ_DUAL_OUTPUT driver. If I change line 203 in MappedSPIFlash.v to

assign MOSI_out = sending && cmd_addr[31]; // was 39

then this driver works with my board, which is equipped with a Winbond W25Q32JV Flash.

Regards, Bernd.

Hi,

Thank you for building this awesome project, I am trying to build the softcore for Icestick and run an example program but I am not able to get any UART output. I verified the core built on the Icestick works by uploading a simple program that blinks the LED onboard, but for some unknown reason I can't get the USB serial to output anything. (hello.prog)

I am building from commit: f681e81

Here is the config I am using, I've disabled everything except, LED, UART and SPI Flash

`define NRV_IO_LEDS          // Mapped IO, LEDs D1,D2,D3,D4 (D5 is used to display errors)
// `define NRV_IO_IRDA          // In IO_LEDS, support for the IRDA on the IceStick (WIP)
`define NRV_IO_UART          // Mapped IO, virtual UART (USB)
// `define NRV_IO_SSD1351       // Mapped IO, 128x128x64K OLED screen
// `define NRV_IO_MAX7219       // Mapped IO, 8x8 led matrix
`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space. Can be used to run code from SPI flash.

Thank You

learn-fpga/FemtoRV$ make ICESUGAR
...
make[2]: Leaving directory '/home/flag/fpga_stuff/learn-fpga/FemtoRV/FIRMWARE/CRT'
==== Generated femtorv32 libs.
make[1]: Leaving directory '/home/flag/fpga_stuff/learn-fpga/FemtoRV/FIRMWARE'
make: *** No rule to make target 'FIRMWARE/firmware.hex', needed by 'ICESUGAR.synth'. Stop.

Since they were written with the SSD1351 in mind, some demo programs do not look good on the SSD1331.

It would be very nice to have GDB debug support over JTAG using the existing work in DM/DMI/OpenOCD. A good example where the RISC-V debug module was added to the Ibex RV32IMC can be found in these last three commits:

https://github.com/majbthrd/ibex/commits/add_debug

Specifically:

majbthrd/ibex@371c4bc

It is very nice to build/upload and visually start debugging (for example VSCode) within 1 second.

NRV_RESET_ADDR seems to be ignored, the device still starting from address zero.
Do we need longer inititialization time for the BRAMs, or is it something else ?

Hello Bruno,

according to the IceStick Tutorial, I executed “make ICESTICK”. This leads to the following error message on my system (Ubuntu 18.04):

/home/bernd/fpga/mue/project/riscv/femtorv_2102/learn-fpga/FemtoRV/FIRMWARE//TOOLCHAIN/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-as -march=rv32i -mabi=ilp32 -defsym SSD1351=1 -defsym ICE_STICK=1 -I/home/bernd/fpga/mue/project/riscv/femtorv_2102/learn-fpga/FemtoRV/FIRMWARE//LIBFEMTOGL -I/home/bernd/fpga/mue/project/riscv/femtorv_2102/learn-fpga/FemtoRV/FIRMWARE//LIBFEMTORV32 -I/home/bernd/fpga/mue/project/riscv/femtorv_2102/learn-fpga/FemtoRV/FIRMWARE//LIBFEMTOC ssd1351_1331.S -o ssd1351_1331.o
make[2]: *** No rule to make target 'ssd1351_1331_init.o', needed by 'libfemtorv32.a'. Stop.

Since there is no ssd1351_1331_init.c, I removed the dependency in LIBFEMTORV32/Makefile
and the libs were compiled.

If I run “make ICESTICK” again, I get the next error message, which indicates, that the firmware.hex is missing:

==== Generated femtorv32 libs.
make[1]: Leaving directory '/home/bernd/fpga/mue/project/riscv/femtorv_2102/learn-fpga/FemtoRV/FIRMWARE'
yosys -DICE_STICK -q -p "synth_ice40 -relut -top femtosoc -json femtosoc.json" RTL/femtosoc.v
Warning: Yosys has only limited support for tri-state logic at the moment. (RTL/DEVICES/MappedSPIFlash.v:268)
RTL/femtosoc.v:0: ERROR: Can not open file FIRMWARE/firmware.hex for $readmemh.
BOARDS/icestick.mk:11: recipe for target 'ICESTICK.synth' failed
make: *** [ICESTICK.synth] Error 1

Could you please look into this?

Regards, Bernd.

Hi, Bruno, notice that the SSD1351.v SPIFlash.v SDCard.v are actually all spi bus, can we have a general spi controller with CPOL CPHA configable, so that we can drive misc device like difference size spi lcds, sdcard, spi-flash, and other misc devices.
I usually use the iCEZ0mb1e to test my misc spi devices before
https://github.com/abnoname/iceZ0mb1e/blob/master/rtl/simplespi.v

I tried to run the "Quark" version of the core under simulation (icarus) for educational purposes, but encountered a lot of "X" signals. To make it work I had to add the following:

   initial begin
      cycles = 0;
      aluShamt = 0;
      registerFile[0] = 0;
   end

With this change I was able to run some simple programs.

Hi all,
I am trying to program FemtoRV RISC-V Soft IP core on Icestick.I am using ubuntu 18.04 version as my host system.I am connecting Icestick to the host system through USB.I have installed yosys,nextpnr and FPGA standard libraries and pre-requisites necessary to program Icestick.But,I am facing issue with the device detection.I am attaching the screenshot of the error being faced.Kindly suggest suitable solution to the problem

What I am asking for is some details on how to use system bus backpressure signals, so I can integrate quark into my FPGA synthesis and Verilator simulation (ISA tests). I will get through anyway but I like asking in advance so I have a communication channel if I get stuck.

I am developing my own RISC-V CPU in SystemVerilog, and I would like to compare it against femtorv32_quark.v.
I used an unusual coding style for the instruction decoder which is causing logic consumption and timing issues. I am unable to predict which decoder change would provide improvements, what I think would be an optimization results in worse area and timing. I have not used one-hot decoding yet, since I forgot about it after many years working on designs where optimization was not a priority.
Comparing with quark which is codded with a more conventional style would help me understand and debug those issues.

Initially I am using FPGA vendor synthesis tools due to SystemVerilog requirements, but I will try yosys with SystemVerilog enhancements after I fix the major issues. My final target is to use open source tools for both FPGA and ASIC.

If you are still reading, I have a few questions and comments regarding the quark RTL, which I must say after reviewing it has a low WTF to code line ratio :).
I noticed separate adders are used for addition/subtraction and then the two results are multiplexed. There is also a separate adder for the load/store address. And as I remember a separate PC incrementer and an adder for branches/jumps.
Did you try different adder configurations to optimize timing and FPGA resource utilization?

While I have problems optimizing my unusual instruction decoder, I had some success optimizing adders and datapath multiplexers. My CPU is designed to execute all instructions in a single clock cycle without exceptions. At a minimum I need 2 adders, one for PC increment and branch, and another for everything else, ADD/SUB, branch compare, load/store address and jumps. I was able to see some good area vs. timing compromises by adding extra adders for each immediate value (branch, load, store).

I will run some of those optimization experiment on quark too and will give you some feedback.

Find a way of plugging a keyboard and a mouse (either USB, or PS/2 if USB is too complicated)

Tried to wire PWR to reset (since it is active low, with NRV_NEGATIVE_RESET defined) without success.
Keeping F2 for now, but it would be more intuitive to have PWR for that (and leaving F2 for user interaction / games)

Programs that call femtosoc_tty_init() then printf() do not display anything on the SSD1331 screen (but it works on the SSD1351).

When unplugging and replugging a design with a UART, the UART no longer sends data to the virtual terminal.

• observed on the IceStick
• does not seem to happen on the ULX3S

For now, ESP32 is deactivated (to let the FPGA access the SDCard), would be good to have a way of toggling this, through a bit in a HW register, and a special command, so that we could flash over Wifi, and send programs to the SDCard over Wifi.

Nore: ESP32 can also be used to drive bluetooth peripherals !
https://github.com/dan-rodrigues/ulx3s-bluetooth-gamepad

Add a UART to the FOMU (needs a USB core + UART over USB)

I had to do some tweaks to install the open-source toolchain for the Arty board that I'd like to share, and hopefully the wiki can be updated

$PRJXRAY and $LEARN_FPGA should refer respectively to prjxray directory and learn-fpga directory as previously specifed in git clone command

prjxray should be installed with setup.py
$ sudo python3 $PRJXRAY/setup.py install

same for fasm
$ sudo python3 $PRJXRAY/third_party/fasm/setup.py install

Path needs to point to "utils" directory so fasm2frames.py is found
$ PATH=$PATH:$PRJXRAY/utils/

in makeit.sh, change fasm2frames to fasm2frames.py

$ cd $LEARN_FPGA/Basic/ARTY/ARTY_blink
$ vi ./makeit.sh
$ ./makeit.sh

It toook in my machine about 20 seconds :)

Develop an I2C driver for the M5Stack keyboard and for the Keyboard FeatherWing

@Mecrisp experienced problems with the run from SPI flash mode.

Sometimes on the ULX3S I get random characters from the UART.
To reproduce: start FIRMWARE/EXAMPLES/tty_OLED.c
(or use the left arrow in the "commander" GUI to start the shell)

Hi to all
Thanks for this compact package, I greatly appreciate that i got everything running on my icebreaker board with basically two to three commands.
I am now searching for information how to add my own peripheral.
I need to instantiate two instances of my module. Every single module needs two pins for input and output via PMOD interface talking to the external world, one clock source (main CPU clock will be fine) and it creates single 32-bit register to be read from the CPU.

I still didn't found how the IO pins are allocated, i have them in .pcf file with some names, but I don't know how to direct it to the module.

The implementation of the module was tested with simple testbench acting as top verilog module with every IO connected to pins.

Thank you for a bit of help.

There is (a lot of) room for improvement in the SPI flash controller:

• use a DDR block instead of freq/2 clock
• use faster SPI modes
• use dual IO SPI mode
• check whether the pins for quadspi are wired on the IceStick

Coming back to this after a couple of months and installing new versions of everything (Litex/yosys/nextptr) from github, and now it won't compile (yosys error):

~/learn-fpga/LiteX$ python3 -m boards.radiona_ulx3s_ex --device LFE5U-85F --with-oled --sdram-module MT48LC16M16 --cpu-type femtorv --cpu-variant petitbateau --build --load --ecppack-compress

[snip]
Info:           ECLKBRIDGECS:     0/    2     0%
Info:                   DCSC:     0/    2     0%
Info:             TRELLIS_FF:  3536/83640     4%
Info:           TRELLIS_COMB: 13702/83640    16%
Info:           TRELLIS_RAMW:   131/10455     1%

ERROR: Cell 'wifi_en$tr_io' cannot be bound to bel 'X0/Y47/PIOB' since it is already bound to cell 'wifi_gpio0$tr_io'
0 warnings, 1 error
Traceback (most recent call last):
  File "/usr/lib/python3.9/runpy.py", line 197, in _run_module_as_main
    return _run_code(code, main_globals, None,
  File "/usr/lib/python3.9/runpy.py", line 87, in _run_code
    exec(code, run_globals)
  File "/home/matt/github_cloned/learn-fpga/LiteX/boards/radiona_ulx3s_ex.py", line 138, in <module>
    main()
  File "/home/matt/github_cloned/learn-fpga/LiteX/boards/radiona_ulx3s_ex.py", line 131, in main
    builder.build(**builder_kargs, run=args.build)
  File "/home/matt/litex_2022/litex/litex/soc/integration/builder.py", line 350, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/matt/litex_2022/litex/litex/soc/integration/soc.py", line 1198, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/matt/litex_2022/litex/litex/build/lattice/platform.py", line 43, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/matt/litex_2022/litex/litex/build/lattice/trellis.py", line 236, in build
    _run_script(script)
  File "/home/matt/litex_2022/litex/litex/build/lattice/trellis.py", line 174, in _run_script
    raise OSError("Error occured during Yosys/Nextpnr's script execution.")
OSError: Error occured during Yosys/Nextpnr's script execution.

Commenting out

     soc.add_ESP32()

in radiona_ulx3s_ex.py made everything happy again....