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ariane

Ariane is a 6-stage RISC-V CPU

block-nvdla-sifive

cores-swerv-eh2

cores-swerv-el2

curly-duck

test for verilog_obfuscator

e200_opensource

The Ultra-Low Power RISC Core

eda_featurecolle

A collection of license features from a varity of EDA vendors

freedom

Source files for SiFive's Freedom platforms

freedom-e-sdk

Open Source Software for Developing on the Freedom E Platform

itri-opendla

Express DLA implementation for FPGA, revised based on NVDLA.

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

learning-nvdla-notes

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

opene906

OpenXuantie - OpenE906 Core

piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

pulpino

An open-source microcontroller system based on RISC-V

rcnn-nvdla-sjtu-demo

NVDLA Shanghai Jiaotong Univerity DEMO using RCNN. C++ and Python implementation for embedded system.

redtail

Perception and AI components for autonomous mobile robotics.

ribsnetwork

riscv

riscv-formal

RISC-V Formal Verification Framework

riscv-openocd

riscv-tools

RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)

rocket-chip

Rocket Chip Generator

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

sw

NVDLA SW

tiny-dnn

header only, dependency-free deep learning framework in C++11