ben-marshall / verilog-dot Goto Github PK
View Code? Open in Web Editor NEWA simple dot file / graph generator for Verilog syntax trees.
A simple dot file / graph generator for Verilog syntax trees.
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$ ./src/verilog-dot --ast --hierarchy -o test1.dot ../tests/simple.v
Segmentation fault (core dumped)
$ ./src/verilog-dot -o test1.dot ../tests/simple.v
Usage: ./verilog-dot [args] [input files]
Options:
--ast - Draw the abstract syntax tree.
--hierarchy - Draw the module instance hierarchy.
-h, --help - Print this message and quit.
-v, --verbose - Print verbose information messages.
[-o | --output] <FILE PATH>
- Specifiy the output file path. By default,
is the input path, with .dot appended.
Example:
./verilog-dot -v -o module-graph.dot my_module.v
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Doing the following edit in commenting out line 95 in ../src/main.c shows there is an issue in how the command line options are being used :
89 int main(int argc, char ** argv)
90 {
91 shell_args * args = parse_args(argc,argv);
92 if(args -> draw_ast == BOOL_FALSE &&
93 args -> module_hierarchy == BOOL_FALSE){
94 free(args);
95 //print_help(BOOL_TRUE);
96 }
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$ make
[ 66%] Built target verilogparser
Scanning dependencies of target verilog-dot
[ 73%] Building C object src/CMakeFiles/verilog-dot.dir/main.c.o
Linking C executable verilog-dot
[ 93%] Built target verilog-dot
[100%] Built target parser
$ ./src/verilog-dot -o test1.dot ../tests/simple.v
line 0 - ERROR: syntax error, unexpected ANY, expecting ATTRIBUTE_START or KW_MACROMODULE or KW_MODULE or KW_PRIMITIVE
- ''
ERROR: Failed to parse input file: ./src/verilog-dot
ERROR Could not open file for reading: -o
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Seems as if the program name is being taken as the input file from the command line invocation
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$ ./src/verilog-dot --ast --hierarchy -v -o test1.dot ../tests/simple.v
Output File: test1.dot
../tests/simple.v
Segmentation fault (core dumped)
$ ./src/verilog-dot -v -o test1.dot ../tests/simple.v
Output File: test1.dot
line 0 - ERROR: syntax error, unexpected ANY, expecting ATTRIBUTE_START or KW_MACROMODULE or KW_MODULE or KW_PRIMITIVE
- ''
ERROR: Failed to parse input file: ./src/verilog-dot
ERROR Could not open file for reading: -v
$ ./src/verilog-dot --ast --hierarchy -o test1.dot ../tests/simple.v
Segmentation fault (core dumped)
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Typo in the following:
Example:
./verilog-dot -v -o module-graph.dot my_module.v
$> ./src/verilog-dot -v -o my-new-graph.v ../tests/simple.v
Input File: ../tests/simple.v
Output File: my-new-graph.dot
Parsing of input file successful.
Dot file writing complete!
$>
$> dot -Tsvg ../tests/my-new-graph.dot > my-new-graph.svg
Corrected should be:
Example:
./verilog-dot -v -o module-graph.dot my_module.v
$> ./src/verilog-dot -v -o my-new-graph.dot ../tests/simple.v
Input File: ../tests/simple.v
Output File: my-new-graph.dot
Parsing of input file successful.
Dot file writing complete!
$>
$> dot -Tsvg ../tests/my-new-graph.dot > my-new-graph.svg
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