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Some bitshifts are done on ints rather than longs:

• setting v flag (incorrectly sets v)
• movz and movk (breaks movz/k with shift)

I assembled and executed a program with the lone instruction
STUR X1, [X2, #20]

In the graphical output, the MemRead signal is 1 and the MemWrite is 0. Shouldn't MemWrite be 1 here?

It appears that rather than writing PC +4 to the LR, the tool instead writes the address of the function to LR. This causes functions to loop endless rather than returning.

717 registerFile[destReg] = immediate << quadrantShift;
726 registerFile[destReg] = registerFile[destReg] | (immediate << quadrantShift);

These two lines of code have immediate as int types. This causes issues with the results of MOVK and MOVZ. Some of the observed issues:

MOVZ X1, 0x8000, LSL #16 will result in X1 having a value of 0xffffffff80000000, this is a sign extended result where sign extension should not happen.

MOVZ X1, 0x8000, LSL #32 will result in X1 having a value of 0x8000.

MOVZ X1, 0x8000, LSL #48 will result in X1 having a value of 0xffffffff80000000, this is wrong in sign and distance.

I can not suggest a fix as I do not have a Java build environment handy.

Hi,
I have encountered issues that arise from the setting of the C and V flags when trying to use conditional branches (B.HI and B.LE)

The sequence
movz x1, #36
movz x2, #54
subs x5, x1, x2
b.LE lse
does not work properly. The V flag is set but 36-54 = -18 is not a signed overflow.

The sequence
movz x1, #54
movz x2, #36
subx x5, x1, x2
b.GT gtr
does not work properly as 54-36=18 does not set the carry bit as it should.

In the setVflag(long result, long op1, long op2) {
replacing

with
Vflag = (((long) op1 & 0x80000000L) == ((long) op2 & 0x80000000L)) && ((long) result != (long)op1;
may work but I don't have the experience with GWT projects to rebuild.

I haven't had a chance to figure the issue with setting the C flag in the other scenario.

Thanks,
Dave