For more information and updates: http://alexforencich.com/wiki/en/verilog/ethernet/start
GitHub repository: https://github.com/alexforencich/verilog-ethernet
Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes full MyHDL testbench with intelligent bus cosimulation endpoints.
For IP and ARP support only, use ip_complete (1G) or ip_complete_64 (10G).
For UDP, IP, and ARP support, use udp_complete (1G) or udp_complete_64 (10G).
ARP handling logic with parametrizable retry timeout parameters.
ARP handling logic with parametrizable retry timeout parameters and 64 bit datapath for 10G Ethernet.
Basic LRU cache for ARP entries. Parametrizable depth.
ARP frame receiver.
ARP frame receiver with 64 bit datapath for 10G Ethernet.
ARP frame transmitter.
ARP frame transmitter with 64 bit datapath for 10G Ethernet.
Ethernet frame check sequence calculator.
Ethernet frame check sequence calculator with 64 bit datapath for 10G Ethernet.
Ethernet frame check sequence checker.
Ethernet frame check sequence inserter.
Ethernet frame arbitrated muliplexer with 8 bit data width for gigabit Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with eth_arb_mux.py.
Ethernet frame arbitrated muliplexer with 8 bit data width for 10G Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with eth_arb_mux_64.py.
Ethernet frame receiver.
Ethernet frame receiver with 64 bit datapath for 10G Ethernet.
Ethernet frame transmitter.
Ethernet frame transmitter with 64 bit datapath for 10G Ethernet.
Ethernet frame demuliplexer with 8 bit data width for gigabit Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with eth_demux.py.
Ethernet frame demuliplexer with 64 bit data width for 10G Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with eth_demux_64.py.
Gigabit Ethernet MAC with GMII interface.
Gigabit Ethernet MAC with GMII interface and FIFOs.
Gigabit Ethernet MAC RX with GMII interface.
Gigabit Ethernet MAC TX with GMII interface.
10G Ethernet MAC with XGMII interface.
10G Ethernet MAC with XGMII interface and FIFOs.
10G Ethernet MAC RX with XGMII interface.
10G Ethernet MAC TX with XGMII interface.
Ethernet frame muliplexer with 8 bit data width for gigabit Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with eth_mux.py.
Ethernet frame muliplexer with 64 bit data width for 10G Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with eth_mux_64.py.
GMII PHY interface and clocking logic.
IPv4 block with 8 bit data width for gigabit Ethernet. Manages IPv4 packet transmssion and reception. Interfaces with ARP module for MAC address lookup.
IPv4 block with 64 bit data width for 10G Ethernet. Manages IPv4 packet transmssion and reception. Interfaces with ARP module for MAC address lookup.
IP frame arbitrated muliplexer with 8 bit data width for gigabit Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with ip_arb_mux.py.
IP frame arbitrated muliplexer with 8 bit data width for 10G Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with ip_arb_mux_64.py.
IPv4 module with ARP integration.
Top level for gigabit IP stack.
IPv4 module with ARP integration and 64 bit data width for 10G Ethernet.
Top level for 10G IP stack.
IP frame receiver.
IP frame receiver with 64 bit datapath for 10G Ethernet.
IP frame transmitter.
IP frame transmitter with 64 bit datapath for 10G Ethernet.
IP frame demuliplexer with 8 bit data width for gigabit Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with ip_demux.py.
IP frame demuliplexer with 64 bit data width for 10G Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with ip_demux_64.py.
IP frame muliplexer with 8 bit data width for gigabit Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with ip_mux.py.
IP frame muliplexer with 64 bit data width for 10G Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with ip_mux_64.py.
Fully parametrizable combinatorial parallel LFSR/CRC module.
UDP block with 8 bit data width for gigabit Ethernet. Manages UDP packet transmssion and reception.
UDP block with 64 bit data width for 10G Ethernet. Manages UDP packet transmssion and reception.
UDP frame arbitrated muliplexer with 8 bit data width for gigabit Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with udp_arb_mux.py.
UDP frame arbitrated muliplexer with 8 bit data width for 10G Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with udp_arb_mux_64.py.
UDP module with IPv4 and ARP integration.
Top level for gigabit UDP stack.
UDP module with IPv4 and ARP integration and 64 bit data width for 10G Ethernet.
Top level for 10G UDP stack.
UDP frame receiver.
UDP frame receiver with 64 bit datapath for 10G Ethernet.
UDP frame transmitter.
UDP frame transmitter with 64 bit datapath for 10G Ethernet.
UDP frame demuliplexer with 8 bit data width for gigabit Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with udp_demux.py.
UDP frame demuliplexer with 64 bit data width for 10G Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with udp_demux_64.py.
UDP frame muliplexer with 8 bit data width for gigabit Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with udp_mux.py.
UDP frame muliplexer with 64 bit data width for 10G Ethernet. Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with udp_mux_64.py.
tdata : Data (width generally DATA_WIDTH)
tkeep : Data word valid (width generally KEEP_WIDTH, present on _64 modules)
tvalid : Data valid
tready : Sink ready
tlast : End-of-frame
tuser : Bad frame (valid with tlast & tvalid)
rtl/arp.v : ARP handling logic
rtl/arp_64.v : ARP handling logic (64 bit)
rtl/arp_cache.v : ARP LRU cache
rtl/arp_eth_rx.v : ARP frame receiver
rtl/arp_eth_rx_64.v : ARP frame receiver (64 bit)
rtl/arp_eth_tx.v : ARP frame transmitter
rtl/arp_eth_tx_64.v : ARP frame transmitter (64 bit)
rtl/eth_arb_mux.py : Ethernet frame arbitrated multiplexer generator
rtl/axis_eth_fcs.v : Ethernet FCS calculator
rtl/axis_eth_fcs_64.v : Ethernet FCS calculator (64 bit)
rtl/axis_eth_fcs_insert.v : Ethernet FCS inserter
rtl/axis_eth_fcs_check.v : Ethernet FCS checker
rtl/eth_arb_mux_2.v : 2 port Ethernet frame arbitrated multiplexer
rtl/eth_arb_mux_4.v : 4 port Ethernet frame arbitrated multiplexer
rtl/eth_arb_mux_64.py : Ethernet frame arbitrated multiplexer generator (64 bit)
rtl/eth_arb_mux_64_2.v : 2 port Ethernet frame arbitrated multiplexer (64 bit)
rtl/eth_arb_mux_64_4.v : 4 port Ethernet frame arbitrated multiplexer (64 bit)
rtl/eth_axis_rx.v : Ethernet frame receiver
rtl/eth_axis_rx_64.v : Ethernet frame receiver (64 bit)
rtl/eth_axis_tx.v : Ethernet frame transmitter
rtl/eth_axis_tx_64.v : Ethernet frame transmitter (64 bit)
rtl/eth_demux.py : Ethernet frame demultiplexer generator
rtl/eth_demux_4.v : 4 port Ethernet frame demultiplexer
rtl/eth_demux_64.py : Ethernet frame demultiplexer generator (64 bit)
rtl/eth_demux_64_4.v : 4 port Ethernet frame demultiplexer (64 bit)
rtl/eth_mac_1g.v : Gigabit Etherent GMII MAC
rtl/eth_mac_1g_fifo.v : Gigabit Etherent GMII MAC with FIFO
rtl/eth_mac_1g_rx.v : Gigabit Etherent GMII MAC RX
rtl/eth_mac_1g_tx.v : Gigabit Etherent GMII MAC TX
rtl/eth_mac_10g.v : 10G Etherent XGMII MAC
rtl/eth_mac_10g_fifo.v : 10G Etherent XGMII MAC with FIFO
rtl/eth_mac_10g_rx.v : 10G Etherent XGMII MAC RX
rtl/eth_mac_10g_tx.v : 10G Etherent XGMII MAC TX
rtl/eth_mux.py : Ethernet frame multiplexer generator
rtl/eth_mux_2.v : 4 port Ethernet frame multiplexer
rtl/eth_mux_4.v : 4 port Ethernet frame multiplexer
rtl/eth_mux_64.py : Ethernet frame multiplexer generator (64 bit)
rtl/eth_mux_64_2.v : 4 port Ethernet frame multiplexer (64 bit)
rtl/eth_mux_64_4.v : 4 port Ethernet frame multiplexer (64 bit)
rtl/gmii_phy_if.v : GMII PHY interface
rtl/ip.v : IPv4 block
rtl/ip_64.v : IPv4 block (64 bit)
rtl/ip_arb_mux.py : IP frame arbitrated multiplexer generator
rtl/ip_arb_mux_4.v : 4 port IP frame arbitrated multiplexer
rtl/ip_arb_mux_64.py : IP frame arbitrated multiplexer generator (64 bit)
rtl/ip_arb_mux_64_4.v : 4 port IP frame arbitrated multiplexer (64 bit)
rtl/ip_complete.v : IPv4 stack (IP-ARP integration)
rtl/ip_complete_64.v : IPv4 stack (IP-ARP integration) (64 bit)
rtl/ip_eth_rx.v : IPv4 frame receiver
rtl/ip_eth_rx_64.v : IPv4 frame receiver (64 bit)
rtl/ip_eth_tx.v : IPv4 frame transmitter
rtl/ip_eth_tx_64.v : IPv4 frame transmitter (64 bit)
rtl/ip_demux.py : IP frame demultiplexer generator
rtl/ip_demux_4.v : 4 port IP frame demultiplexer
rtl/ip_demux_64.py : IP frame demultiplexer generator (64 bit)
rtl/ip_demux_64_4.v : 4 port IP frame demultiplexer (64 bit)
rtl/ip_mux.py : IP frame multiplexer generator
rtl/ip_mux_4.v : 4 port IP frame multiplexer
rtl/ip_mux_64.py : IP frame multiplexer generator (64 bit)
rtl/ip_mux_64_4.v : 4 port IP frame multiplexer (64 bit)
rtl/lfsr.v : Generic LFSR/CRC module
rtl/udp.v : UDP block
rtl/udp_64.v : UDP block (64 bit)
rtl/udp_arb_mux.py : UDP frame arbitrated multiplexer generator
rtl/udp_arb_mux_4.v : 4 port UDP frame arbitrated multiplexer
rtl/udp_arb_mux_64.py : UDP frame arbitrated multiplexer generator (64 bit)
rtl/udp_arb_mux_64_4.v : 4 port UDP frame arbitrated multiplexer (64 bit)
rtl/udp_complete.v : UDP stack (IP-ARP-UDP)
rtl/udp_complete_64.v : UDP stack (IP-ARP-UDP) (64 bit)
rtl/udp_ip_rx.v : UDP frame receiver
rtl/udp_ip_rx_64.v : UDP frame receiver (64 bit)
rtl/udp_ip_tx.v : UDP frame transmitter
rtl/udp_ip_tx_64.v : UDP frame transmitter (64 bit)
rtl/udp_demux.py : UDP frame demultiplexer generator
rtl/udp_demux_4.v : 4 port UDP frame demultiplexer
rtl/udp_demux_64.py : UDP frame demultiplexer generator (64 bit)
rtl/udp_demux_64_4.v : 4 port UDP frame demultiplexer (64 bit)
rtl/udp_mux.py : UDP frame multiplexer generator
rtl/udp_mux_4.v : 4 port UDP frame multiplexer
rtl/udp_mux_64.py : UDP frame multiplexer generator (64 bit)
rtl/udp_mux_64_4.v : 4 port UDP frame multiplexer (64 bit)
transfer with header data
__ __ __ __ __ __ __
clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__
______________ ___________
hdr_ready \_________________/
_____
hdr_valid ________/ \_____________________________
_____
hdr_data XXXXXXXXX_HDR_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
___________ _____ _____
tdata XXXXXXXXX_A0________X_A1__X_A2__XXXXXXXXXXXX
___________ _____ _____
tdata XXXXXXXXX_A0________X_A1__X_A2__XXXXXXXXXXXX
___________ _____ _____
tkeep XXXXXXXXX_K0________X_K1__X_K2__XXXXXXXXXXXX
_______________________
tvalid ________/ \___________
_________________
tready ______________/ \___________
_____
tlast __________________________/ \___________
tuser ____________________________________________
two byte transfer with sink pause after each byte
__ __ __ __ __ __ __ __ __
clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
_____ _________________
tdata XXXXXXXXX_D0__X_D1______________XXXXXXXXXXXXXXXXXXXXXXXX
_____ _________________
tkeep XXXXXXXXX_K0__X_K1______________XXXXXXXXXXXXXXXXXXXXXXXX
_______________________
tvalid ________/ \_______________________
______________ _____ ___________
tready \___________/ \___________/
_________________
tlast ______________/ \_______________________
tuser ________________________________________________________
two back-to-back packets, no pauses
__ __ __ __ __ __ __ __ __
clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
_____ _____ _____ _____ _____ _____
tdata XXXXXXXXX_A0__X_A1__X_A2__X_B0__X_B1__X_B2__XXXXXXXXXXXX
_____ _____ _____ _____ _____ _____
tkeep XXXXXXXXX_K0__X_K1__X_K2__X_K0__X_K1__X_K2__XXXXXXXXXXXX
___________________________________
tvalid ________/ \___________
________________________________________________________
tready
_____ _____
tlast ____________________/ \___________/ \___________
tuser ________________________________________________________
bad frame
__ __ __ __ __ __
clk __/ \__/ \__/ \__/ \__/ \__/ \__
_____ _____ _____
tdata XXXXXXXXX_A0__X_A1__X_A2__XXXXXXXXXXXX
_____ _____ _____
tkeep XXXXXXXXX_K0__X_K1__X_K2__XXXXXXXXXXXX
_________________
tvalid ________/ \___________
______________________________________
tready
_____
tlast ____________________/ \___________
_____
tuser ____________________/ \___________
Running the included testbenches requires MyHDL and Icarus Verilog. Make sure that myhdl.vpi is installed properly for cosimulation to work correctly. The testbenches can be run with a Python test runner like nose or py.test, or the individual test scripts can be run with python directly.
tb/arp_ep.py : MyHDL ARP frame endpoints
tb/axis_ep.py : MyHDL AXI Stream endpoints
tb/eth_ep.py : MyHDL Ethernet frame endpoints
tb/gmii_ep.py : MyHDL GMII endpoints
tb/ip_ep.py : MyHDL IP frame endpoints
tb/udp_ep.py : MyHDL UDP frame endpoints
tb/xgmii_ep.py : MyHDL XGMII endpoints
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