GPGPU processor supporting RISCV-V extension, developed with Chisel HDL.

Copyright 2021-2022 by International Innovation Center of Tsinghua University, Shanghai

The micro-architecture overview of Ventus(承影) is shown below. Chinese docs is here. English version will come soon.

For ISA simulator and riscv-gnu-toolchain, see ventus-gpgpu-isa-simulator and ventus-riscv-gnu-toolchain

The tutorial of Chisel development environment configuration comes from chipsalliance/playground: chipyard in mill :P

0. Install dependencies and setup environments:

• Arch Linux pacman -Syu --noconfirm make parallel wget cmake ninja mill dtc verilator git llvm clang lld protobuf antlr4 numactl
• Nix nix-shell

1. Init and update dependences

make init
make patch

2. IDE support make bsp # generate IDE bsp
3. to generate verilog file, use make verilog. The output file is GPGPU_axi_top.v
4. to run tests, use make tests. Output waveform file is at test_run_dir

We refer to some open-source design when developing Ventus GPGPU.