GPGPU processor supporting RISCV-V extension, developed with Chisel HDL.
Copyright 2021-2022 by International Innovation Center of Tsinghua University, Shanghai
The micro-architecture overview of Ventus(承影) is shown below. Chinese docs is here. English version will come soon.
For ISA simulator and riscv-gnu-toolchain, see ventus-gpgpu-isa-simulator and ventus-riscv-gnu-toolchain
The tutorial of Chisel development environment configuration comes from chipsalliance/playground: chipyard in mill :P
- Install dependencies and setup environments:
- Arch Linux
pacman -Syu --noconfirm make parallel wget cmake ninja mill dtc verilator git llvm clang lld protobuf antlr4 numactl
- Nix
nix-shell
- Init and update dependences
make init
make patch
- IDE support
make bsp # generate IDE bsp
- to generate verilog file, use
make verilog
. The output file isGPGPU_axi_top.v
- to run tests, use
make tests
. Output waveform file is attest_run_dir
We refer to some open-source design when developing Ventus GPGPU.
Sub module | Source | Detail |
---|---|---|
CTA scheduler | MIAOW | Our CTA scheduler module is based on MiaoW ultra-threads dispatcher. |
L2Cache | block-inclusivecache-sifive | Our L2Cache design is inspired by Sifive's block-inclusivicache |
Multiplier | XiangShan | We reused Array Multiplier in XiangShan. FPU design is also inspired by XiangShan. |
Instructions, Config, ... | rocket-chip | Some modules are sourced from RocketChip |