This is the third project of CSC 3050, Computer Architecture in LGU. A 5-stage pipelined CPU in verilog is implemented in this project.

Below is the file tree of this project:

.
├── ALU.v
├── Adder.v
├── BranchForward.v
├── BranchUnit.v
├── CPU.v
├── ControlUnit.v
├── ForwardingUnit.v
├── HazardUnit.v
├── InstructionRAM.v
├── MainMemory.v
├── RAM_OUTPUT
├── RegisterFile.v
├── SignExtend.v
├── StageRegs.v
├── Suber.v
├── cpu_tb.v
├── cpu_test/
├── makefile
└── readme.md

This project mainly follows the architecture of the implementation of the 5-stage pipelined CPU described in the textbook with a few modifications, which support more instructions(as required):

Data transfer instructions: 
- lw, sw
Arithmetic instructions:
- add, addu, addi, addiu, sub, subu
Logical instructions: 
- and, andi, nor, or, ori, xor, xori
Shifting instructions:
- sll, sllv, srl, srlv, sra, srav
Branch/Jump instructions:
- beq, bne, slt
- j, jr, jal

Baically, to compile the project, just type

> make

in your terminal. The test samples were downloaded from the blackboard. To test the 8 samples, type

> make 
> make auto -i

This will test all the eight samples and generate a file DIFFERENCE containing all the outputs generated by diff(I think there is one mistake in the official sample DATA_RAM1.txt in which the output of xori may be wrong).

Specifically, if you want to just test specific sample, you can just type, e.g.,

> make 
> make test1

This will run the diff in the terminal.

This project supports data and control forwarding and completes all the basic situations described in the textbook. For more details, you can just refer to the report.