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FreeRTOS for Cadence Tensilica HIFI 4 DSP on R329, D1-H, T113 With GCC Compiler

Makefile 0.72% C 78.43% Assembly 4.98% HTML 14.31% JavaScript 0.94% CSS 0.62%

dsp freertos xtensa hifi4

freertos-hifi4-dsp's Introduction

FreeRTOS-HIFI4-DSP

⚠ NOT official RTOS SDK and Compiler, NOT Support DSP feature

FreeRTOS for Cadence Tensilica HIFI 4 DSP, With GCC Compiler

About Compiler

Cadence Tensilica HIFI 4 use Xtensa Xplorer and XCC for development. This Project does not support XCC or Xtensa Xplorer, We use GCC for Compile.

How to build

Clone codes

git clone https://github.com/YuzukiHD/FreeRTOS-HIFI4-DSP.git

Download Compiler and unzip it to tools
make

Firmware Loader

SyterKit

SyterKit provide hifi4 loader: https://github.com/YuzukiHD/SyterKit/tree/main/board/100ask-d1-h/load_hifi4

Here is a U-Boot Driver to load firmware to HIFI4 DSP

https://github.com/YuzukiHD/FreeRTOS-HIFI4-DSP/tree/master/host/uboot-driver/dsp

freertos-hifi4-dsp's People

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1847123212 duanzhonghuan vendorapp greenvic lysjtucn mfkiwl flyingcys mark4app loulansuiye kamejoko80 yyznefu

freertos-hifi4-dsp's Issues

uboot 加载 dsp.elf 报错

开发板是 Sipeed Lichee RV，系统镜像是 LicheeRV_Tina_dock_hdmi_8723ds.img ，利用了 Tina Linux 中魔改的 uboot，其中包括了 bootr 命令来给 DSP 加载 firmware。

uboot 命令行下加载 firmware 报错

=> echo $(boot_dsp0)
sunxi_flash read 45000000 ${dsp0_partition};bootr 45000000 0 0
=> sunxi_flash read 45000000 ${dsp0_partition};bootr 45000000 0 0
dsp0:uart config fail
dsp0:gpio init config fail
dsp0:find section err

修改 bootdelay

在 /etc/fw_env.config 中添加 /dev/by-name/env /dev/by-name/env-redund
之后通过 fw_setenv 编辑 bootdelay

制作 dsp 分区

dd if=dsp.elf of=/dev/mmcblk0p5

编译出错问题,src/main.c:13:10: fatal error: xtutil.h: No such file or directory

你好!
编译DSP程序时,出现xtutil.h没有找到.把相应用到的都注释掉后可以正常编译.这个不会影响系统效果吧!

Allwinner T113-s3 DSP static DRAM interleave fix proposal.

Then I fill data ram of embedded DSP, address translation discovered.
You can integrate these functions:

// HiFI4 DSP-viewed address offset translate to host cpu viewwed
static ptrdiff_t xlate_dsp2mpu(ptrdiff_t a)
{
	const ptrdiff_t BANKSIZE = 0x08000u;
	const ptrdiff_t CELLBASE = 0x10000u;
	const ptrdiff_t CELLSIZE = 16;
	const ptrdiff_t cellbank = (a - CELLBASE) / BANKSIZE;
	const ptrdiff_t cellrow = (a - CELLBASE) % BANKSIZE / CELLSIZE;	// 16 bytes granularity
	const unsigned cellpos = (a % CELLSIZE);	// 16 bytes granularity

	if (a < CELLBASE)
		return a;	/* translation not needed. */

	return CELLBASE +
			cellbank * BANKSIZE +
			CELLSIZE * ((cellrow % 2) ? (cellrow / 2) + (BANKSIZE / CELLSIZE / 2) : cellrow / 2) +
			cellpos;
}

static void copy2dsp(uint8_t * pdspmap, const uint8_t * pcpu, unsigned offs, unsigned size)
{
	for (; size --; ++ offs)
	{
		pdspmap [xlate_dsp2mpu(offs)] = pcpu [offs];
	}
}

static void zero2dsp(uint8_t * pdspmap, unsigned offs, unsigned size)
{
	for (; size --; ++ offs)
	{
		pdspmap [xlate_dsp2mpu(offs)] = 0x00;
	}
}