Comments (4)
cliffordwolf
commented on July 22, 2024
There are a couple of open todo items that I'd like to address first. As soon as this is done I'll tag a release.
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olofk
commented on July 22, 2024
Cool. I'll prepare the stuff on the FuseSoC side in the meantime
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impedimentToProgress
commented on July 22, 2024
I second this. Hopefully FuseSoC has a AXI4-Wishbone bridge. It would be nice to have a RISC-V SoC with DDR and Ethernet support.
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cliffordwolf
commented on July 22, 2024
Just tagged v1.0.
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Related Issues (20)
- Bug: TRAP after >8000 clock cycles HOT 6
- ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.
- calling custom IRQ instructions in C code
- read delay of PICORV32_REGS must be 0? HOT 1
- Bug report: fence instruction raises instruction trap
- Dynamically Setting PROGADDR_RESET HOT 1
- What is PCPI base address? HOT 5
- [Bug report] Attempt to access a non-implemented CSR should raise an illegal instruction
- [Bug report] Some mandatory CSRs are not implemented
- [Bug report] Performance counters are not writable
- [Bug report] Performance counters reads are incorrectly required to be of csrrs opcode
- [Bug report] Wrong performance counter address
- Building a pure RV32I Toolchain
- Running new Assembly Code on PicoRV32 HOT 1
- how to access picorv32_pcpi_mul from software? HOT 2
- Why it doesn't has memory module in picoRV code? Why in the testench?
- JAL instruction not working as expected
- wbm_sel_o == 0 during read transactions
- Is this project still maintained?
- Issue with branch while using BRAM. HOT 1
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