Comments (6)
Same here. No error messages at all.
from picorv32.
I got a little bit more information after chainging the picorv32.v file:
`
Built with Verilator 4.038 2020-07-11.
Recommended: Verilator 4.0 or later.
MISALIGNED WORD: 0x00000152
MISALIGNED WORD: 0x00000152
TRAP after 8223 clock cycles
ERROR!
%Error: testbench.v:271: Verilog $stop
`
from picorv32.
hello, i managed to get it build by using this command
make TOOLCHAIN_PREFIX=riscv32-unknown-elf-
:)
Edit: doesn't work after a make clean ..., so not the solution
Edit2: found that need to set path to opt
export PATH=/opt/riscv32im/bin:$PATH
here for im
from picorv32.
I'm getting the same thing. I was able to get around it using version 10.2.0 here:
https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/
Not sure what the problem is but it seems to not work with newer versions of gcc
from picorv32.
Got around this issue on GCC 13.2.0 doing the following to the Makefile:
diff --git a/Makefile b/Makefile
index d7027e3..feda8a7 100644
--- a/Makefile
+++ b/Makefile
@@ -15,8 +15,8 @@ TEST_OBJS = $(addsuffix .o,$(basename $(wildcard tests/*.S)))
FIRMWARE_OBJS = firmware/start.o firmware/irq.o firmware/print.o firmware/hello.o firmware/sieve.o firmware/multest.o firmware/stats.o
GCC_WARNS = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings
GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion
-TOOLCHAIN_PREFIX = $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)i/bin/riscv32-unknown-elf-
-COMPRESSED_ISA = C
+TOOLCHAIN_PREFIX ?= $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)i/bin/riscv32-unknown-elf-
+COMPRESSED_ISA =
# Add things like "export http_proxy=... https_proxy=..." here
GIT_ENV = true
@@ -116,7 +116,7 @@ firmware/start.o: firmware/start.S
$(TOOLCHAIN_PREFIX)gcc -c -mabi=ilp32 -march=rv32im$(subst C,c,$(COMPRESSED_ISA)) -o $@ $<
firmware/%.o: firmware/%.c
- $(TOOLCHAIN_PREFIX)gcc -c -mabi=ilp32 -march=rv32i$(subst C,c,$(COMPRESSED_ISA)) -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
+ $(TOOLCHAIN_PREFIX)gcc -c -mabi=ilp32 -march=rv32im$(subst C,c,$(COMPRESSED_ISA)) -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
$(TOOLCHAIN_PREFIX)gcc -c -mabi=ilp32 -march=rv32im -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
from picorv32.
It was solved by modifying the start.S to fix the alignment in issue #210 . rethhelo also opened a PR to fix the problem #218 . "This PR forces irq_regs to always be aligned with .balign 0x200, by doing this solves the problem." in start.S
from picorv32.
Related Issues (20)
- ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.
- calling custom IRQ instructions in C code
- read delay of PICORV32_REGS must be 0? HOT 1
- Bug report: fence instruction raises instruction trap
- Dynamically Setting PROGADDR_RESET HOT 1
- What is PCPI base address? HOT 5
- [Bug report] Attempt to access a non-implemented CSR should raise an illegal instruction
- [Bug report] Some mandatory CSRs are not implemented
- [Bug report] Performance counters are not writable
- [Bug report] Performance counters reads are incorrectly required to be of csrrs opcode
- [Bug report] Wrong performance counter address
- Building a pure RV32I Toolchain
- Running new Assembly Code on PicoRV32 HOT 1
- how to access picorv32_pcpi_mul from software? HOT 2
- Why it doesn't has memory module in picoRV code? Why in the testench?
- JAL instruction not working as expected
- wbm_sel_o == 0 during read transactions
- Is this project still maintained?
- Issue with branch while using BRAM. HOT 1
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from picorv32.