重要的文字描述：
The modified primitive loads MR elements of A and NR elements of B, and performs MRxNR multiply-accumulate operations. The maximum values of MR and NR are limited by the number of registers and other details of processor architecture. But on most modern systems, they are large enough to make the operation compute-bound, and all high-performance matrix-matrix multiplication implementations build upon this primitive, commonly called ### PDOT (panel dot product) microkernel.

paper link: https://www.academia.edu/22937999/High_performance_image_processing_on_FPGAs
1 In each clock cycle the entire circuit executes, and an entire code block can
be viewed as one large, specialized instruction [7].

The SA-C compiler provides one-step compilation to host executable and FPGA configurations ,
这里的one step, 让我想起了 compiler 分为3种

• 1. one pass compiler
• 2. two pass compiler
• 3. multiple pass compiler.

其中有一个图介绍编译器

Figure 1. SA-C Compilation system

After optimization, the program is convertedto a combination of low-level dataflow graphs(DFGs) and host code. DFGs are then compiledto VHDL code via Abstract Hardware Architec-ture (AHA) graphs. The VHDL code is synthe-sized and place-and-routed to FPGAs by commer-cial software tools

Figure 8. Overview of a typical architecture of CNN accelerator based on an embedded FPGA platform.

Figure 9. Typical architecture of processing element

from：https://cdn.intechopen.com/pdfs/60223.pdf