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surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

synadm

Command line admin tool for Synapse (Matrix reference homeserver)

tatum

Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

telethon

Pure Python 3 MTProto API Telegram client library, for bots too!

tg_owt

uhdm

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

usb2sniffer-qt

usb3_pipe

USB3 PIPE interface for Xilinx 7-Series / Lattice ECP5

usbsniffer

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

waybar

Highly customizable Wayland bar for Sway and Wlroots based compositors. :v: :tada:

wotop

Web on top of any protocol

yosys

Yosys Open SYnthesis Suite

yosys-symbiflow-plugins

Plugins for Yosys developed as part of the SymbiFlow project.