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//提供一个不一样的思路,两个always并行
module top_module(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );
assign cout[0] = a[0] & b[0] | a[0] & cin | b[0] & cin;
assign sum[0] = a[0] ^ b[0] ^ cin;
integer i, j;
always @ (*)
begin
for (i=1; i<100; i++)
begin
sum[i] = a[i] ^ b[i] ^ cout[i-1];
end
end
always @ (*)
begin
for(i=1; i<100; i++)
begin
cout[i] = a[i] & b[i] | a[i] & cout[i-1] | b[i] & cout[i-1];
end
end
endmodule
Your top_module will instantiate two copies of add16 (provided), each of which will instantiate 16 copies of add1 (which you must write). Thus, you must write two modules: top_module and add1.
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different);
assign out_both = {{in[3] & in[2]}, {in[2] & in[1]}, {in[1] & in[0]}};
assign out_any = {{in[3] | in[2]}, {in[2] | in[1]}, {in[1] | in[0]}};
assign out_different = {{in[0] ^ in[3]}, {in[3] ^ in[2]}, {in[2] ^ in[1]}, {in[1] ^ in[0]}};
endmodule
按照 Verilog-Practice/0_Getting Started/01_Step_one.v 答案運行之後,雖然答案正確但會出現這樣的警告:
Warning (13024): Output pins are stuck at VCC or GND
This warning says that an output pin never changes (is "stuck"). This can sometimes indicate a bug if the output pin shouldn't be a constant. If this pin is not supposed to be constant, check for bugs that cause the value being assigned to never change (e.g., assign a = x & ~x;)
請問要如何避免這樣的警告?
謝謝!
The first bcd_fadder
instance may be merged into the for loop as by tuning the genvar i
and a larger temp signal c
.
module top_module(
input [15:0] a, b,
input cin,
output cout,
output [15:0] sum );
wire [4:0] c;
assign c[0] = cin;
assign cout = c[4];
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin : adders
bcd_fadd the_bcd_fadders (
.a(a[i*4+3 : i*4]),
.b(b[i*4+3 : i*4]),
.cin(c[i]),
.cout(c[i+1]),
.sum(sum[i*4+3 : i*4])
);
end
endgenerate
endmodule
file location:
https://github.com/xiaop1/Verilog-Practice/blob/master/2_Circuits/072_Bcdadd4.v
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