This repository contains the solutions for the assignments from the 'Methodologies for System Level Design Modeling' course (ECE5723) taken at Worcester Polytechnic Institute - WPI in the Fall 2020. The repository includes 7 projects, namely:

1 - Logic Design, VHDL Modeling, and Testbench.

• A frequency divider circuit.
  

2 - RT Level Design and C++ Logic Modeling.

• An average calculator circuit (in C++).
  

3 - C++ RT Level Design and Modeling.

• A transition counter circuit.
  

4 - SystemC RTL Design.

• An average calculator circuit (in SystemC).
  

5 - SystemC Channels.

• A multiway shared switch circuit.
  

6 - SystemC Transaction Level Modeling.

• An interconnect circuit.
  

7 - Logic review, HDL Background, RT Level Modeling with C++, SystemC RTL Modeling.

• A 1011 Moore sequence detector circuit.
  
• An 8-bit, 4-function ALU circuit.
  
• A processing element for Taylor series approximate calculation of 1/(1-x).
  

During the course, various digital hardware systems were modeled using C++ and SystemC.

The detailed information about the projects is contained in the attached reports placed in the corresponding subfolders.

1. Visual Studio 2019 - IDE [visualstudio.microsoft.com].
2. draw.io - for drawing diagrams [https://app.diagrams.net/].
3. WaveDrom - for drawing waveforms [https://wavedrom.com/].
4. GTKWave - VCD viewer [http://gtkwave.sourceforge.net/].

For the projects 4-6, SystemC-2.3.3 (includes TLM) C++ library was used [https://www.accellera.org/downloads/standards/systemc].
The corresponding subfolders contain the file named 'Microsoft.Cpp.Win32.user.props'. This file contains the data about dependencies.
This propert sheet may be exported into Visual Studio 2019 through the built-in Property Manager.

Prof. Zainalabedin Navabi ([email protected]) for teaching the course, formulating the tasks, as well as for the valuable discussions on Methodologies for System Level Design Modeling.

The files are published with the permission of Prof. Navabi.