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View Code? Open in Web Editor NEWA framework that can automatically locate inconsistent instructions between real devices and emulators for ARM
License: BSD 3-Clause "New" or "Revised" License
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The tool does not analyze whole conditions specified in the ASL code
The tool does not analyze whole conditions specified in the ASL code. For instance, the method isUnpredictable() of InstEncoding (in instrs2asl.py):
>>> all_encodings['aarch32_ADD_i_T3_A'].isUnpredictable('11110001000000100000110000100100')
if (d == 15 && !setflags) || n == 15 then UNPREDICTABLE
d == 15 Converted to: d == 15
n == 15 Converted to: n == 15
d == 15 Converted to: d == 15
// Armv8-A removes UNPREDICTABLE for R13
whether 11110001000000100000110000100100 meets d == 15 Converted to: d == 15 for aarch32/ADD_i/T3_A
related variable d
init variable d = BitVec('d',32)
related variable Rd
True
In the above example the tool does not consider the value of the setflags variable at all.
Crashes on MRS and MSR instructions
When launching the generate_insts_from_asl() function of instrs2asl.py, the tool crashes on MRS and MSR instructions:
Traceback (most recent call last):
File "<stdin>", line 8, in <module>
File "/XXX/mra_tools/bin/instrs2asl.py", line 981, in generate_insts
for condition in self.conditions:
File "/XXX/mra_tools/bin/instrs2asl.py", line 1137, in solve
File "<string>", line 1
SYSm == SYSm<0>
SyntaxError: invalid syntax
Instruction streams incorrectly recognized as unpredictable
The method isUnpredictable() of InstEncoding (in instrs2asl.py) incorrectly recognizes instruction streams as unpredictable. For example:
>>> all_encodings['aarch32_ADD_i_T3_A'].isUnpredictable('11110001000000100000110000100100')
if (d == 15 && !setflags) || n == 15 then UNPREDICTABLE
d == 15 Converted to: d == 15
n == 15 Converted to: n == 15
d == 15 Converted to: d == 15
// Armv8-A removes UNPREDICTABLE for R13
whether 11110001000000100000110000100100 meets d == 15 Converted to: d == 15 for aarch32/ADD_i/T3_A
related variable d
init variable d = BitVec('d',32)
related variable Rd
True # <-- False expected
According to the ARM documentation, the stream 11110001000000100000110000100100 is a valid and predictable ADD (immediate) T3 instruction.
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