Focusing on post-manufacturing test analysis:

1. We have developed an open-source test toolcahin called UT-DATE
2. We have designed and incorporated several testability methods to test the SAYAC embedded system, including:
   • Processor
   • Memory
   • Interconnect

Several existing Design for Test (DFT) techniques are incorporated into the SAYAC processor to make it testable and evaluate its testability for post-manufacturing faults, considering stuck-at-fault models.

After several design modifications to make SAYAC test-ready, the following DFT techniques have been incorporated:

• Single and multiple scan testing
• Built-in self-test (BIST) architectures, including RTS & STUMPS
• Boundary-scan IEEE 1149.1 standard.

Memory blocks of SAYAC, including RAM, instruction ROM, and register file have been tested for memory fault models through:

• Memory BIST architectures, and
• Boundary scan IEEE 1149.1 architecture,
• Considering MARCH algorithms.

The data bus and address bus interconnects of the JTAG-compliant SAYAC processor are tested using the EXTEST instruction of the IEEE 1149.1 standard.

• The code folders are organized according to the structure of the report document.

• Running some projects (like LBIST and MBIST) requires using VHDL 2008, as hierarchical access to signals is a part of the VHDL 2008 standard. To use VHDL 2008 in Modelsim, follow these steps:

  From the view tab
  Select the properties option
  Go to the VHDL tab
  Select the Use 1076-2008 option.

• Stable Documentation: https://github.com/UTehran-NavabiLab/SAYAC-system-Testing/tree/main/docs
• Test & Testability Codes: https://github.com/UTehran-NavabiLab/SAYAC-system-Testing/tree/main/codes
• SAYAC System as DUT: https://github.com/RHESGroup/SAYAC-Embedded-Processor
• Test Toolchain: https://pypi.org/project/ut-date/
• Bugs and Feature Requests: https://github.com/UTehran-NavabiLab/SAYAC-system-Testing/issues

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