ultraembedded / core_spiflash Goto Github PK

Github: http://github.com/ultraembedded/cores

This component is a basic AXI4 to SPI Flash interface (1-bit read-only mode). Useful for executing bootloaders stored in FPGA configuration SPI PROMs.

• Single bit SPI Flash support (3 address cycles).
• AXI4 slave supporting singles and bursts.
• Supports SPI-Flash devices which support read page command (0x03).
• Supports CPOL=0, CPHA=0 SPI (Mode 0) only.

Verified under simulation and tested on FPGA (XC7A35T with N25Q64A SPI-PROM).

• parameter CLK_DIV - Clock divider ratio for clk_i -> spi_clk_o (spi_clk = clk_i / (1 + CLK_DIV))
• parameter tSLCH_CYCLES - Number of clk_i cycles from chip select to SPI transfer start
• parameter tSLSL_CYCLES - Number of clk_i cycles chip select must remain in-active between transfers

• Slice LUTs: 341
• Slice Registers: 162
• BlockRAM: 0
• DSP: 0