How to improve data port speed? about pcileech-fpga HOT 5 CLOSED

BTW I'm using USB3.2 GEN1 cable&USB3.2 GEN1 interface.

from pcileech-fpga.

FIFO side of this chip is 32-bits @ 100MHz, i.e. 400MB/s dynamically shared between rx/tx.

Protocol overhead in PCILeech (in the implemention I've got) is 1 dword per / 7 dwords of data transmitted. i.e. x 7/8

PCIe TLP overhead for larger rx is 12bytes per 128 bytes received, i.e. x 128 / (128 + 12).

400 * 7/8 * 128/(128+12) = 320MB/s theoretical when only bulk receiving data. Add to this that some time is required for transmitting data over this shared bus as well it will eat up max performance.

People on some really fast Intel computers have reported close to 250MB/s on optimal workloads, and this is very close to the theoretical max.

In reality 180MB/s isn't that bad. It's close to the practical max of the FT601 chip. If you can find a better chip please let me know.

from pcileech-fpga.

Thanks for your quick answer! According your answer,could i get a conclusion that cable does effect the speed? Or it effect with CPU&cable? Before u answer I just found some information from a DMA board provider,they said use 3.2gen2 cable&interface could improve speed to 240MByte/s.

from pcileech-fpga.

I don't think USB 3.2 will make a difference in itself since the FT601 is not capable of it. But a nice higher speed USB controller and a really fast CPU definitely makes some changes. And as you mention speeds around 240 MB/s have been possible, and it's very close to the theoretical maximum... so there isn't a whole lot more I can do as things stand right now...

from pcileech-fpga.

Ok thanks i'll keep research this part!

from pcileech-fpga.