Advice Request: Ported project to new board and 1Gbit Ethernet, how can I make it faster? about pcileech-fpga HOT 5 CLOSED

@ufrisk Yeah that's completely reasonable. I'll continue doing some testing on it and get back to you.

from pcileech-fpga.

It may be issues in your fpga design, or more likely there would be issues in the leechcore.dll/so file as well. Timeout and delays tuned for the slower NeTV2.

Of interest are functions named: DeviceFPGA_UDP_* and the NeTV2 profile. I don't know if this is your issue, but it's where I'd start looking at least.

from pcileech-fpga.

Hey, as an update to this, I did play around with the leechcore delays and sizes to no real effect. I dumped some UDP traffic and did some analysis on the throughput and the UDP stream was achieving nearly 100% of the 1G ethernet line rate.

This lead me to do some overhead calculations to see what the actual maximum throughput of the system could be. For my target system, I was only getting 64 bytes per CplD, so after calculating out the TLP and TCP/IP framing overhead I see that the maximum memory throughput is essentially already being achieved here.

Therefore, the only way to improve on this would be to upgrade to 2.5G or 10G ethernet.

Thanks again!

from pcileech-fpga.

Also, would you be interested in taking a PR for this Alinx development board? It uses the RGMII core that was recently published by fpga-cores.

from pcileech-fpga.

I'd be very happy to include a link to your repo from the main project page. I could add it as a "community supported device" (similar to legacy supported device table, but separate) or if you wish to submit a PR for this link.

Accepting the PR with the actual FPGA project into the main project would also increase my maintenance burden with new updated releases and such and I'm not too keen on that.

from pcileech-fpga.