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Tung Hoang's Projects

memtorch icon memtorch

A Simulation Framework for Memristive Deep Learning Systems

mlp_neurosim_v3.0 icon mlp_neurosim_v3.0

Benchmark framework of synaptic device technologies for a simple neural network

nutshell icon nutshell

RISC-V SoC designed by students in UCAS

openlane icon openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

opentitan icon opentitan

OpenTitan: Open source silicon root of trust

pillars icon pillars

An integrated CGRA design framework

pulp icon pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

py-hpi icon py-hpi

Python/Simulator integration using procedure calls

riscv icon riscv

RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

riscv-dv icon riscv-dv

SV/UVM based open-source instruction generator for RISC-V processor verification

riscv-ml icon riscv-ml

Machine Learning project using RISC-V and NVDLA on Linux

rramspec icon rramspec

RRAMSpec - A RRAM Area, Energy and Timing Generator

rsd icon rsd

RSD: RISC-V Out-of-Order Superscalar Processor

sgi-stl-docs icon sgi-stl-docs

Standard template library (STL) documentation from SGI. (Mirror)

siliconcompiler icon siliconcompiler

SiliconCompiler is an open source compiler framework that automates translation from source code to silicon.

skywater-pdk icon skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

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