Combine logic locking with secure multiparty computation for privacy-preserving intellectual property verification. Transform Verilog (2005) code (i.e., locked netlists) into "Bristol Fashion" MPC Circuits and run them using MP-SPDZ.
The SoK outlining this framework will appear in 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS) (the preprint can be accessed here) and here. You can cite this article as follows:
@INPROCEEDINGS{IOLTS:Mouris23mploc,
author = "Dimitris Mouris and
Charles Gouert and
Nektarios Georgios Tsoutsos",
booktitle = "2023 IEEE 29th International Symposium on On-Line Testing
and Robust System Design (IOLTS)",
title = "{MP$\ell\circ$C: Privacy-Preserving IP Verification using
Logic Locking and Secure Multiparty Computation}",
year = "2023",
volume = "",
number = "",
pages = "1-7",
doi = ""
}
sudo apt-get install automake build-essential clang cmake git libboost-dev \
libboost-thread-dev libntl-dev libsodium-dev libssl-dev libtool m4 python3 \
texinfo yasm yosysClone this repository:
git clone --recurse-submodules [email protected]:jimouris/mploc.gitcd MP-SPDZ
make setup
make Programs/Circuits
make -j8 all
cd ..Create the EDIF files with Yosys:
$ yosys
yosys> read_verilog Programs/Verilog/4_bit_adder.v
yosys> synth
yosys> abc -g XOR,AND
yosys> write_edif Programs/EDIF/4_bit_adder.edif
yosys> exitConvert the edif file to a Bristol fashion circuit:
python src/edif2bristol.py --edif Programs/EDIF/4_bit_adder.edif --out Programs/Circuits/4_bit_adder.txtFrom the MP-SPDZ directory run:
mkdir -p Player-Data
echo 4 > Player-Data/Input-P0-0
echo 2 0 > Player-Data/Input-P1-0./MP-SPDZ/compile.py 4_bit_adder
./MP-SPDZ/Scripts/semi.sh 4_bit_adder
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