Topic: veriloga Goto Github
Some thing interesting about veriloga
Some thing interesting about veriloga
veriloga,A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley
User: akashlevy
veriloga,Digital Loop Filter Realization
User: ax0080
veriloga,The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuction is to generate the specific waveforms according to your setting.And the setting is done in the python code (main.py), which will facilitate greatly the coding works.
User: colsonzhang
veriloga,Verilog-A test block for estimating noise and offset of a dynamic comparator in a transient simulation. Uses the Confidence-Boosting concept published at NEWCAS 2024.
User: joschua-conrad
veriloga,This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
User: muhammadaldacher
Home Page: https://drive.google.com/open?id=1TUYCLbdZC5S4dQVAxZmoUjMQPiLFntPe
veriloga,This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
User: muhammadaldacher
veriloga,This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
User: muhammadaldacher
veriloga,Language support in Visual Studio Code for VerilogA
User: nikacvet
veriloga,Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)
User: rpm2003rpm
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