数字电路课程设计，洗衣机
华科数字电路课程设计，题目选择的是洗衣机，难度为甲
这里说明一下设计时的坑，首先是状态应当尽量少，然后将具体的任务分配给底层模块执行 还有就是如果功能比较单一，就尽量不要使用双状态机，否则状态机间的通信会非常麻烦，容易出错
不能综合的几种情况： 1.使用了异步逻辑电路实现状态机（verilog不支持异步时序逻辑） 2.同一个变量被不同always块修改 3.always块的敏感列表过多（过多的锅不在语言语法上，在硬件上，因为有些硬件不支持）
几点设计建议： 1.模块之间的通信时，将变量reg存放在底层，顶层传出wire即可 2.同步时序逻辑电路always块内尽量只有clk 3.同步时序逻辑电路内使用<= 非租塞赋值，这样时钟到来时信号能够一起加载，而且可以避免竞争问题
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