An verilog implementation of a 16 bit processor, codenamed Artemis. This implements a simple prototype processor with a full reg file, ALU, instruction set decoder, prog counter and other basic features. The instruction set is detailed in the FPU-assembler repo. For more details on the implementation, watch the presentation I did on it here. Also here is a little simulation clip from the simulated performance of the processor.

• I want to extend the processor to have memory-mapped I/O
• Need to move from the Xilinx workflow to a iCE open source workflow
• Just slowly add more and more features and optimizations